CY7C1049DV33-10VXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1049DV33-10VXI

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049DV33

Switching Waveforms (continued)

Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[18]

ADDRESS

CE

tWC

tSCE

WE

DATA I/O

ADDRESS

CE

WE

DATA I/O

tSA

NOTE 19

tAW

tHA

tPWE

tHZWE

tSD

DATA VALID

Figure 7. Write Cycle No. 3 (CE Controlled)[18, 20]

tHD

tLZWE

tWC

tSCE

tSA

tSCE

tAW

tHA

tPWE

tSD

tHD

DATA VALID

Notes

18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

19. During this period the IOs are in the output state and input signals must not be applied.

20. Data IO is high impedance if OE = VIH.

Document Number: 38-05475 Rev. *G

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