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DM9102A

Single Chip Fast Ethernet NIC controller

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DM9102A

Single Chip Fast Ethernet NIC controller

Table of Contents

General Description ............................................................. 1

Block Diagram...................................................................... 1

Features ............................................................................... 4

Pin Configuration: DM9102A 128pin QFP.......................... 5

Pin Configuration: DM9102A 128pin TQFP ....................... 6

Pin Description ..................................................................... 7

- PCI Bus and CardBus Interface Signals......................... 7

- Boot ROM and EEPROM Interface ................................ 8

T Multiplex Mode ................................................................ 8

T Direct Mode.................................................................... 10

- LED Pins......................................................................... 11

- Network Interface ........................................................... 12

- Miscellaneous Pins......................................................... 12

- Power Pins ..................................................................... 13

- Note: LED Mode ............................................................ 13

Register Definition.............................................................. 14

✧ PCI Configuration Registers.......................................... 14

Key to Default..................................................................... 14

T Identification ID............................................................... 15

T Command & Status........................................................ 15

T Revision ID ..................................................................... 17

T Miscellaneous Function ................................................. 18

T I/O Base Address........................................................... 18

T Memory Mapped Base Address.................................... 19

T Subsystem Identification ................................................ 19

T CardBus CIS Pointer...................................................... 20

T Expansion ROM Base Address..................................... 21

T Capabilities Pointer......................................................... 21

T Interrupt & Latency Configuration .................................. 22

T Device Specific Configuration Register......................... 22

T Power Management Register........................................ 23

T Power Management Control/Status .............................. 24

✧ Control and Status Register (CR).................................. 25

Key to Default..................................................................... 25

1. System Control Register (CR0)..................................... 26

2. Transmit Descriptor Poll Demand (CR1)...................... 27

3. Receive Descriptor Poll Demand (CR2) ....................... 27

4. Receive Descriptor Base Address (CR3) ..................... 27

5. Transmit Descriptor Base Address (CR4) .................... 28

6. Network Status Report Register (CR5)......................... 28

2

7. Network Operation Register (CR6)............................... 30

8. Interrupt Mask Register (CR7)...................................... 32

9. Statistical Counter Register (CR8)................................ 33

10. PROM & Management Access Register (CR9) ........ 34

11. Programming ROM Address Register (CR10) .......... 35

12. General Purpose Timer Register (CR11)................... 35

13. PHY Status Register (CR12) ...................................... 35

14. Sample Frame Access Register (CR13).................... 36

15. Sample Frame Data Register (CR14) ........................ 36

16. Watching & Jabber Timer Register (CR15)................ 36

✧ CardBus Status Changed Register .............................. 39

1. Function Event Register: (offset 80h)............................ 39

2. Function Event Mask Register: (offset 84h).................. 39

3. Function Present State Register: (offset 88h)............... 39

4. Function Force Event Register: (offset 8Ch) ................ 40

✧ PHY Management Register Set ................................... 41

Key To Default ................................................................... 41

Basic Mode Control Register (BMCR)

- Register 0......................................................................... 42

Basic Mode Status Register (BMSR)

- Register 1......................................................................... 43

PHY ID Identifier Register #1 (PHYIDR1)

- Register 2......................................................................... 44

PHY ID Identifier Register #2 (PHYIDR2)

- Register 3......................................................................... 44

Auto-negotiation Advertisement Register (ANAR)

- Register 4......................................................................... 44

Auto-negotiation Link Partner Ability Register (ANLPAR) -

Register 5........................................................................... 45

Auto-negotiation Expansion Register (ANER)

- Register 6......................................................................... 46

DAVICOM Specified Configuration Register (DSCR)

- Register 10....................................................................... 46

DAVICOM Specified Configuration and Status Register

(DSCSR) - Register 11...................................................... 47

10Base-T Configuration/Status (10BTSCRCSR)

- Register 12....................................................................... 48

Functional Description ....................................................... 49

✧ System Buffer Management ......................................... 49

1. Overview........................................................................ 49

2. Data Structure and Descriptor List ................................ 49

3. Buffer Management: Chain Structure Method.............. 49

5. Descriptor List: Buffer Descriptor Format...................... 49

(a). Receive Descriptor Format......................................... 49

Final

Version: DM9102A-DS-F03

August 28, 2000

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