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DM9102A

Single Chip Fast Ethernet NIC controller

Unspecified 

27

30

31

33

2

20

34

48

121,122,123,124,126,127,

128,1,6,7,10,

11,13,14,16,

17,38,39,40,

41,43,44,47,

49,50,51,54,

55,56,57,59,

60

STOP#

PERR#

SERR#

PAR

C/BE3#

C/BE2#

C/BE1#

C/BE0#

AD31~AD0

DM9102A

Single Chip Fast Ethernet NIC controller

destination address of the data transfer is recognized by a

target.

I/O Stop

This signal is asserted low by the target device to request the

master device to stop the current transaction.

I/O Parity Error

The DM9102A as a master or slave will assert this signal low

to indicate a parity error on any incoming data.

I/O System Error

This signal is asserted low when address parity is detected

with PCICS bit31 (detected parity error) Is enabled. The

system error asserts two clock cycles after the falling address

if an address parity error is detected.

I/O Parity

This signal indicates even parity across AD0~AD31 and

C/BE0#~C/BE3# including the PAR pin. This signal is an

output for the master and input for the slave device. It is

stable and valid one clock after the address phase.

I/O Bus Command/Byte Enable

During the address phase, these signals define the bus

command or the type of bus transaction that will take place.

During the data phase these pins indicate which byte lanes

contain valid data. C/BE0# applies to bit7-0 and C/BE3#

applies to bit31-24.

I/O Address & Data

These are multiplexed address and data bus signals. As a

bus master, the DM9102A will drive address during the first

bus phase. During subsequent phases, the DM9102A will

either read or write data expecting the target to increment its

address pointer. As a target, the DM9102A will decode each

address on the bus and respond if it is the target being

addressed.

Boot ROM and EEPROM Interface (Including multiplex mode or direct mode)

Multiplex mode

Pin No.

Pin Name

I/O

Description

128QFP/128TQFP

62,63,64,65,

BPAD0~BPAD7 I/O, LI Boot ROM address and data bus (bits 0~7)

66,67,68,69

(BPAD7/LEDMODE)

Boot ROM address and data multiplexed lines bits 0~7. In

MUX mode, there are two consecutive address cycles, these

lines contain the boot ROM address pins 7~2, out_enable and

write_enable of Boot ROM in the first cycle; and these lines

contain address pins 15~8 in second cycle.

After the first two cycles, these lines contain data bit 7~0 in

consective cycles.

BPAD1 is also a reset latch pin. It is Boot ROM address and

data bus when normal operation. When at power on reset, it is

used to pull up or down externally through a resister to select

8

Final

Version: DM9102A-DS-F03

August 28, 2000

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