DM9102A Ver la hoja de datos (PDF) - Unspecified
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DM9102A Datasheet PDF : 77 Pages
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Features
T Integrated Fast Ethernet MAC, Physical Layer and
transceiver in one chip.
T 128pin QFP/128pin TQFP with CMOS process.
T +3.3V Power supply with +5V tolerant I/O.
T Supports PCI and CardBus interfaces.
T Comply with PCI specification 2.2.
T PCI clock up to 40MHz.
T PCI bus master architecture.
T PCI bus burst mode data transfer.
T Two large independent FIFO; receive FIFO & transmit
FIFO.
T Up to 256K bytes Boot EPROM or Flash interface.
T EEPROM 93C46 interface supports node ID accesses
configuration information and user define message.
T Node address auto-load and reload.
T Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
T Comply with IEEE 802.3u auto-negotiation protocol for
DM9102A
Single Chip Fast Ethernet NIC controller
automatic link type selection.
T Full Duplex/Half Duplex capability.
T Support IEEE 802.3x Full Duplex Flow Control
T VLAN support.
T Comply with ACPI and PCI Bus Power Management.
T Supports the MII (Media Independent Interface).
T Supports Wake-On-LAN function and remote wake-up
(Magic packet, Link Change and Microsoft® wake-up
frame).
T Supports 4 Wake-On-LAN (WOL) signals (active high
pulse, active low pulse, active high , active low ).
T High performance 100Mbps clock generator and data
recovery circuit.
T Digital clock recovery circuit using advanced digital
algorithm to reduce jitter.
T Adaptive equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver.
T Provides Loopback mode for easy system diagnostics.
4
Final
Version: DM9102A-DS-F03
August 28, 2000
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