MX98745 Ver la hoja de datos (PDF) - Macronix International
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MX98745 Datasheet PDF : 36 Pages
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MX98745
6.3 INTERNAL REGISTERS
All the registers can be accessed through MII's MDC and
MDIO. Although XRC II connects to multiple 100-TX
PHY's, they are all identical. Each XRC has only one
PHY address as defined by PHY[4:0] pins (which will be
latched by the rising edge of RESETL, and will be over-
written by the contents of EEPROM whenever EECONF
is set to 1). If multiple XRC's are on the same MDIO bus,
each of them should have different PHY address. Other
non-XRC PHY devices (e.g. T4) are also allowed to be
managed with the same management interface as long
as PHY address of each device is distinct.
Register 0 and 1 are Command and Status registers
which specified in [1]. Additional registers provided by
MX98745 is located from address 16 to 31 (decimal
value). Port Control Registers are located from address
#16 to address #20. These control registers include port
reset control register (#16), Port Scremabler control reg-
ister (#17), Port Enable Control Register (#18), Isolation
Disable Control Register (#19) and Partition Disable Con-
trol Register (#20).
Port Status Registers are located from address #25 to
address #29. These registers include Link Status Regis-
ter (#25), Partition Status Register (#26), Elastic Buffer
Status Register (#27), Jabber Status Register (#28) and
Isolation Status Register (#29).
Register #31 is Configuration Register. Value latched at
the rising edge of RESETL will be stored in this register.
Value on this register will be overwritten by contents of
EEPROM in case EECONF is set to 1 except PMSEL
and TXMII which will be affected only by hardwire set-
ting.
A. Command Register (register #0) (R/W)
Bit(s) Name
Description
R/W
0.15 Reset
1 : PHY reset. A 240ns reset pulse will be generated to
R/W
reset XRC internal logic.
SC
0 : normal operation.
0.14 Loop Back
1 : enable loopback mode.
R/W
0 : disable loopback mode.
The default setting is 0.
0.13 Speed Selection
Forced to 1 and indicate 100 Mb/s.
R
Write 0 to this bit has no effect.
0.12 Auto-Negotiation Enable Forced to 0 and indicate that Auto-Negotiation process
R
is disable.
Write 1 to this bit has no effect.
R/W
0.11 Power Down
1 : power down. COCLK and TXCLK for each port will be R/W
disabled. Clock for Management Block will keep running.
During Power down, all state machines will be reset to its
default state.
0 : normal operation.
0.10 Isolate
1 : electrically Isolate PHY from MII
R/W
0 : normal operation
P/N:PM0427
REV. 1.4, JUL. 8, 1998
12
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