MX98745
D. Scrambler Control Register (register #17) (R/W)
Bit(s)
Name
Description
R/W
17.15:8 Reserved
Write any value to these bits have no effect.
R/W
Written value will be released onto MDIO
whenever Read Command is issued
17.7
ScrenP7
1 : Enable Scrambler/Descrambler at Port 7
R/W
0 : Disable Scrambler/Descrambler at Port 7
The default value after power on is 1.
17.6
ScrenP6
1 : Enable Scrambler/Descrambler at Port 6
R/W
0 : Disable Scrambler/Descrambler at Port 6
The default value after power on is 1.
17.5
ScrenP5
1 : Enable Scrambler/Descrambler at Port 5
R/W
0 : Disable Scrambler/Descrambler at Port 5
The default value after power on is 1.
17.4
ScrenP4
1 : Enable Scrambler/Descrambler at Port 4
R/W
0 : Disable Scrambler/Descrambler at Port 4
The default value after power on is 1.
17.3
ScrenP3
1 : Enable Scrambler/Descrambler at Port 3
R/W
0 : Disable Scrambler/Descrambler at Port 3
The default value after power on is 1.
17.2
ScrenP2
1 : Enable Scrambler/Descrambler at Port 2
R/W
0 : Disable Scrambler/Descrambler at Port 2
The default value after power on is 1.
17.1
ScrenP1
1 : Enable Scrambler/Descrambler at Port 1
R/W
0 : Disable Scrambler/Descrambler at Port 1
The default value after power on is 1.
17.0
ScrenP0
1 : Enable Scrambler/Descrambler at Port 0
R/W
0 : Disable Scrambler/Descrambler at Port 0
The default value after power on is 1.
Table 6-4 Scrambler Control Register Bit Definition
Note : When SCRCTRL is set to 0, contents of this regis-
ter will be disabled.
P/N:PM0427
REV. 1.4, JUL. 8, 1998
15