SC18IS600 Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Lista de partido

SC18IS600

SPI to I2C-bus interface

NXP Semiconductors. 

NXP Semiconductors

SC18IS600

SPI to I2C-bus interface

2 SYSTEM

CLOCK

CYCLES

VDD

P

P very P

strong

weak

weak

pin latch data

VSS

input data

Fig 4. Quasi-bidirectional output configuration

GPIOn,

IOn pin

glitch rejection

002aab882

6.2.1.2 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the pin when the pin latch contains a logic 0. To be used as a logic output, a

pin configured in this manner must have an external pull-up, typically a resistor tied to

VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open-drain pin configuration is shown in Figure 5.

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

pin latch data

VSS

input data

Fig 5. Open-drain output configuration

GPIO pin

glitch rejection

002aab883

6.2.1.3 Input-only configuration

The input-only pin configuration is shown in Figure 6. It is a Schmitt-triggered input that

also has a glitch suppression circuit.

input data

Fig 6. Input-only configuration

GPIO pin

glitch rejection

002aab884

SC18IS600

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 20 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

7 of 30

Share Link: