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SC18IS600

SPI to I2C-bus interface

NXP Semiconductors. 

NXP Semiconductors

SC18IS600

SPI to I2C-bus interface

6.2.4 I2C-bus clock rates register (I2CClk)

This register determines the I2C-bus clock frequency. Various clock rates are shown in

Table 7 for the SC18IS600. The frequency can be determined using Equation 1:

I2C-bus

clock

frequency

=

7---.--3---7---2---8---------1---0----6

4  I2CClk



Hz



(1)

Table 7. I2C-bus clock frequency example at 7.3728 MHz

I2CClk (decimal) I2C-bus clock frequency

5 (minimum)

369 kHz

7

263 kHz

9

204 kHz

19

97 kHz

255 (maximum)

7.2 kHz

6.2.5 I2C-bus time-out register (I2CTO)

The time-out register is used to determine the maximum time that the I2C-bus master is

allowed to complete a transfer before setting an I2C-bus time-out interrupt.

Table 8.

Bit

7:1

0

I2CTO - I2C-bus time-out register (address 0x04) bit description

Symbol

Description

TO[7:1]

Time-out value

TE

Enable/disable time-out function

logic 0 = disable

logic 1 = enable

The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1

will enable the time-out function.

On the SC18IS600 the time-out oscillator operates at 57.6 kHz.

This oscillator is fed into a 16-bit down counter. The down counter’s lower nine bits are

loaded with ‘1’, while the upper seven bits are loaded with the contents of I2CTO.

57.6 kHz

OSCILLATOR

Fig 8. Time-out value

16-BIT DOWN COUNTER

[I2CTO][111111111]

002aab715

time-out

The time-out value is an approximate value.

In the case of arbitration loss, the SC18IS600 will transmit a START condition when the

bus becomes free unless the time-out condition is reached. If the time-out condition is

reached, an interrupt will be generated on the INT pin. The ‘I2C-bus time-out’ status can

be read in I2CStat.

SC18IS600

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 20 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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