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UPD4564323

64M-bit Synchronous DRAM 4-bank, LVTTL

NEC => Renesas Technology 

µPD4564323 for Rev. E

9. Precharge

The precharge command can be issued anytime after tRAS (MIN.) is satisfied.

Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters

the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.

The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is

as follows.

It is depending on the /CAS latency and clock cycle time.

Burst length=4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

/CAS latency = 2

Command

Read

PRE

Hi-Z

DQ

Q1

Q2

Q3

Q4

/CAS latency = 3

Command

Read

PRE

Hi-Z

DQ

Q1

Q2

Q3

Q4

(tRAS must be satisfied)

In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The

tDPL(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks

is calculated by dividing tDPL(MIN.) with clock cycle time.

In summary, the precharge command can be issued relative to reference clock that indicates the last data word is

valid. In the following table, minus means clocks before the reference; plus means time after the reference.

/CAS latency

2

3

Read

–1

–2

Write

+tDPL (MIN.)

+tDPL (MIN.)

Data Sheet M14376EJ2V0DS00

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