4.12 Switching Characteristics—Digital Audio Slave Input Port
tiicckcmd
t iicckl
tiicr
tiicf
t iicckcmd
CLK/SCL
tiicstscl
MISO/SDA
INT
0
1
6
7
8
0
1
6
tiicckh
thddo
A6
A0 R/W ACK MSB
t iicsu
tiich
f iicck
tiicirqh
7
8
tiicstp
LSB
ACK
tiicirql
tiicbft
BUSY/
I2C_SELECT
tiiccbsyl
Figure 4-6. Serial Control Port—I2C Slave Mode Timing
4.12 Switching Characteristics—Digital Audio Slave Input Port
Parameter
SCLK period
SCLK duty cycle
Setup time DAI_Dx 1
Hold time DAI_Dx 1
Slave mode
SCLK active edge to LRCLK transition
LRCLK transition to SCLK active edge
1.All DAI data lines are timed relative to active edge of SCLK
DAI_LRCLK
tdaisstlr
DAI_SCLK
tdaidsu
tdaiclkp
tdaidh
DAI_Dx
DAI_LRCLK
DAI_SCLK
DAI_Dx
Figure 4-7. DAI Port Slave Timing Diagram
Symbol
Tdaiclkp
—
tdaidsu
tdaidh
tdaisstlr
tdaislrts
Min Max Unit
40
—
ns
45
55
%
10
—
ns
5
—
ns
10
—
ns
10
—
ns
tdaislrts
tdaiclkp
19
DS1057F1