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CS48LV12-ENZR

Ultralow Power HD Voice Processors, Featuring SoundClear® Technology

Cirrus Logic 

4.13 Switching Characteristics—Digital Audio Output Port

4.13 Switching Characteristics—Digital Audio Output Port

Parameter

MCLK period

MCLK duty cycle

DAO_SCLK period for Slave mode

DAO_SCLK duty cycle for or Slave mode

Slave Mode

SCLK active edge to LRCLK transition

LRCLK transition to SCLK active edge

DAO_Dx delay from SCLK inactive edge

Symbol

Tdaomclk

—

Tdaosclk

—

tdaosstlr

tdaoslrts

tdaosdv

Min Max Unit

20

—

ns

45

55

%

20

—

ns

40

60

%

10

—

ns

10

—

ns

—

11

ns

LRCLK

SCLK

DAO_Dx

t daoslrts

t daosclk

LRCLK

SCLK

tdaosstlr

DAO_Dx

Figure 4-8. Digital Audio Output (DAO) Port Timing, Slave Mode

tdaosclk

t daosdv

DS1057F1

20

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