IDT70P248L Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
Lista de partido
IDT70P248L Datasheet PDF : 23 Pages
| |||
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
Symbol
ILI
ILO
VOLL
VOHL
VOLL
VOHL
VOLR
VOHR
Parameter
Test Conditions
Input Leakage Current
VDD = 1.8V, VIN = 0V to VDD
Output Leakage Current
CE = VIH, VOUT = 0V to VDD
Output Low Voltage (VDDQL = 3.0V) IOLL = +2mA
Output High Voltage (VDDQL = 3.0V) IOHL = -2mA
Output Low Voltage (VDDQL = 2.5V) IOLL = +2mA
Output High Voltage (VDDQL = 2.5V) IOHL = -2mA
Output Low Voltage
IOLR = +0.1mA
Output High Voltage
IOHR = -0.1mA
Min.
___
___
___
2.1
___
2.0
___
VDD - 0.2V
Max.
1
1
0.4
___
0.4
___
0.2
___
Unit
µA
µA
V
V
V
V
V
V
5675 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ±100mV)
70P258/248
Ind'l Only
Symbol
Parameter
Test Condition
Version
Typ.(1) Max. Unit
IDD Dynamic Operating Current CE = VIL, Outputs Open
(Both Ports Active)
f = fMAX(2)
IND'L
L
15
25 mA
ISB1 Standby Current (Both Ports CER and CEL = VIH, SEMR = SEML = VIH
Inactive)
f = fMAX(2)
IND'L
L
2
8
µA
ISB2 Standby Current (One Port
Inactive, One Port Active)
CE"A" = VIL and CE"B" = VIH(3), Active Port Outputs Open
f = fMAX(2)
IND'L
ISB3
Full Standby Current (Both
Ports Inactive - CMOS Level
Both Ports CEL and CER > VDD - 0.2V,
SEML and SEMR > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V
IND'L
Inputs)
M/S = VDD or VSS(4), f = 0
ISB4 Standby Current (One Port
Inactive, One Port Active -
CMOS Level Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(4)
VIN > VDD - 0.2V or VIN < 0.2V, Active Port Outputs Open
f = fMAX(2)
IND'L
L
8.5
L
2
14 mA
8
µA
L
8.5
14 mA
NOTES:
1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. If M/S = VSS, then fBUSYL = fBUSYR = 0 for full standby mode.
5675 tbl 09
6.642
Share Link: 