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PFS726

High Power PFC Controller with Integrated High-Voltage MOSFET

Power Integrations, Inc 

PFS704-729EG

Pin Functional Description

VOLTAGE MONITOR (V) Pin:

The V pin is tied to the rectified AC rail through an external

resistor. Internal circuitry detects the peak of the input line

voltage which resembles a full-wave rectified waveform. The

rectified high-voltage bus is connected directly to the V pin

voltage through a large resistor (4 MW for PFS70x and PFS71x;

9 MW for PFS72x) to minimize power dissipation and standby

power consumption. A small ceramic capacitor (0.1 mF for

PFS70x and PFS71x; 0.047 mF for PFS72x) is required from the

VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass

any switching noise present on the rectified bus. This pin also

features both brown-in and brown-out protection.

FEEDBACK (FB) Pin:

The FEEDBACK pin is high input-impedance reference terminal

that connects to a feedback resistor network. This pin will also

feature fast overvoltage and undervoltage detection circuitry

that will disengage the internal power MOSFET in the event of a

system fault. A 10 nF capacitor is required between the

FEEDBACK to SIGNAL GROUND pins; this capacitor must be

placed very close to the device on the PCB to bypass any

switching noise. This pin is also used for loop compensation.

BIAS POWER (VCC) Pin:

This is a 10-12 VDC bias supply used to power the IC. The bias

voltage must be externally clamped to prevent the VCC pin

from exceeding 15 VDC.

SIGNAL GROUND (G) Pin:

Discrete components used in the feedback circuit, including

loop compensation, decoupling capacitors for the supply (VCC)

and line-sense (V) must be referenced to the G pin. The

SIGNAL GROUND pin must not be tied to the SOURCE pin.

SOURCE (S) Pin:

This pin is the source connection of the power switch.

DRAIN (D) Pin:

This is the tab and drain connection of the internal power switch.

E Package (eSIP-7G)

Exposed Metal (On Edge)

Internally Connected

to GROUND Pin

Exposed Metal

(On Edge)

Internally

Connected to

DRAIN Pin

1 23 45 7

Figure 2. Pin Configuration.

7 54 32 1

Exposed Pad

(Backside)

Internally

Connected to

DRAIN Pin

(see eSIP-7G

Package

Drawing)

PI-5334-083110

VOLTAGE MONITOR (V)

BIAS POWER (VCC)

DRAIN (D)

INPUT

LINE INTERFACE

Peak

Detector

INTERNAL

SUPPLY

VCC+

MON IVPK Input UV

(IUV-/IUV+)

“Off-time derived with

6 V Input Voltage

Emulation

+

constant Volt-Sec

VO-VIN

-

CINT

7 kHz

Filter

VOFF is a function of the error-voltage (VE) and is used to reduce the average

operating frequency as a function of output power for increased efficiency

(PFS704-716).

(VOFF = 0.8 V for PFS723-729).

IVPK

Frequency

Slide

Transconductance

Internal Error-Amplifier

VE

Reference

FEEDBACK (FB)

VREF

+

-

1 kHz

Filter

MON is the switch current

sense scale factor which

is function of peak line

FBOV

+

- Fast OV

FFBBOUFVF/

Comparator

voltage derived from IVIN

MON IS

+

- UV Comparator

VOFF

Comparator

-

+

Comparator

VE +

Input UV

Latch FBOV/UV

OTP

-

TIMER

SUPERVISOR

The internal derived error-voltage (VE)

regulates the output voltage

CINT

SIGNAL GROUND (G)

Figure 3. Functional Block Diagram.

4

Rev. G 06/15

OTP

SOFT

START

VCC

Sense

FET

Driver

LEB

IS

Power

MOSFET

IOCP

OCP

SOURCE (S)

PI-5333-113010

www.power.com

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