RTL8208 Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8208

REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER

Realtek Semiconductor 

RTL8208

6. Register Descriptions

The first six registers of the MII are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp.

for internal use and are reserved for specific uses.

Register

Description

Default

0

Control Register

3100

1

Status Register

0F49

2

PHY Identifier 1 Register

001C

3

PHY Identifier 2 Register

C883

4

Auto-Negotiation Advertisement Register

05E1

5

Auto-Negotiation Link Partner Ability Register

0001

6

Auto-Negotiation Expansion Register

0000

RO: Read Only

RW: Read/Write

LL: Latch Low until cleared

LH: Latch High until cleared

SC: Self Clearing

6.1 Register0: Control

Reg. bit Name

Description

Mode

0.15

Reset

1=PHY reset. This bit is self-clearing.

RW/SC

0.14

Loopback

This will loopback TXD to RXD and ignore all the activities RW

on the cable media. Valid only for 10Base-T.

1=Enable loopback.

0=Normal operation.

0.13

Spd_Sel

When Nway is enabled, this bit reflects the result of RW

Auto-negotiation. (Read only)

When Nway is disabled, this bit can be set by SMI*.

(Read/Write)

When 100FX is enabled, this bit =1 (Read only)

1=100Mbps.

0=10Mbps.

0.12

Auto Negotiation

This bit can be set through SMI.(Read/Write)

RW

Enable

When 100FX is enabled, this bit =0 (Read only)

1 = Enable Auto-negotiation process.

0 = disable Auto-negotiation process.

0.11

Power Down

1=Power down. All functions will be disabled except RW

SMI.read/write function.

0=Normal operation.

0.10

Isolate

1 = Electrically isolate the PHY from RMII/SMII/SS-SMII. RW

PHY is still able to respond to MDC/MDIO.

0 = Normal operation

0.9

Restart Auto

1=Restart Auto-Negotiation process.

RW/SC

Negotiation

0=Normal operation.

0.8

Duplex Mode

When Nway is enabled, this bit reflects the result of RW

Auto-negotiation. (Read only)

When Nway is disabled, this bit can be set by SMI*.

(Read/Write)

When 100FX is enabled, this bit is determined by the

FX_DUPLEX pin. (Read/Write)

1=Full duplex operation.

0=Half duplex operation.

0.[7:0]

Reserved

*SMI: Serial Management Interface , which is composed of MDC,MDIO, allows MAC to manage PHY.

Default

0

0

1

1

or

0 for 100FX

0

0

0

1

0

2003/04/04

12

Rev.1.97

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