RTL8208 Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8208

REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER

Realtek Semiconductor 

RTL8208

7.3.2 Receive Function

The Manchester decoder converts the incoming serial stream when the circuit detects the signal , and the digital serial stream is

then converted to 2-bit (RMII) or 1-bit (SMII/SS-SMII) data format. The preamble of the incoming stream is stripped off and

regenerated. SFD is generated into RXD once the incoming SFD is detected and data bits entering the elastic buffer are over

threshold.

7.3.3 Link Monitor

The 10Base-T link pulse detection circuit constantly monitors the RXIP/RXIN pins for the presence of valid link pulses.

Auto-polarity is implemented for correcting the detected reverse polarity of the RXIP/RXIN signal pairs.

7.3.4 Jabber

Jabber occurs when TX_EN is asserted over 21ms. Both transmit and loopback functions are disabled once jabber occurs. The

MII Register 1.1 (Jabber detect) bit is set high until jabber disappears and the bit is read again. The Jabber function is supported

in 10-Base-T only, and is not implemented in 100Base-TX. The collision LED of the corresponding port will blink while Jabber

occurs. Jabber is dismissed after TX_EN remains low for at least 500ms.

7.3.5 Loopback

Loopback mode can be achieved by writing to Register 0.14=1. Loopback mode routes transmitted data at the output of NRZ to

the NRZI conversion module, back to the receiving path. This mode is used to check all the device’s connection at the 5-bit

symbol bus, and verify the operation of the phase locked loop.

7.4 100Base-TX

An internal 125MHz clock is generated by an on-chip PLL circuit to synchronize the transmit data or generate the clock signal

for the incoming data stream.

7.4.1 Transmit Function

Upon detection of TX_EN high, the RTL8208 converts RMII/SMII/SS-SMII TXD to 5 bit code-group and substitutes J/K

code-groups for the first 2 code-groups, which are called Start of Stream Delimiter (SSD). 4B5B coding continues for all of the data

as long as TX_EN is asserted high. At the end of TX_EN, T/R code-groups are appended to the last data field, which will be

stripped off at the remote receiving side. During the inter-packet gap, where TX_EN deasserted, IDLE code-groups are transmitted

for the sake of clocking of the remote receiver. The 5-bit serial data stream after 4B5B coding is then scrambled as defined by the

TP-PMD Stream Cipher function to flatten the power spectrum energy such that EMI effects can be significantly reduced.

This multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also

benefits EMI emission. Scrambling is not implemented in 100Base-FX.

7.4.2 Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits. These circuits compensate

for incoming distortion of the MLT-3 signal. An MLT-3 to NRZI, and NRZI to NRZ converter is used to convert analog signals to

digital bit-streams. A PLL circuit is also included to clock data bits exactly with minimum bit error rate. De-scrambler, 5B/4B

decoder and serial-to-parallel conversion circuits follow. CRS_DV is asserted no later than when the SSD

(Start-of-Stream-Delimiter) is detected within a few bits time (delay due to the elastic buffer as mentioned in the RMII section),

and ends toggling once the data in the elastic buffer has been dumped to RXD.

2003/04/04

21

Rev.1.97

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