82077AA-1 Ver la hoja de datos (PDF) - Intel
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82077AA-1 Datasheet PDF : 62 Pages
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82077AA CHMOS Single-Chip Floppy Disk Controller
CONTENTS
PAGE
1 0 INTRODUCTION
7
1 1 Oscillator
8
1 2 Perpendicular Recording Mode
8
2 0 MICROPROCESSOR INTERFACE
8
2 1 Status Data and Control
Registers
8
2 1 1a Status Register A
(SRA PS 2 Mode)
8
2 1 1b Status Register A
(SRA Model 30 Mode)
8
2 1 2a Status Register B
(SRB PS 2 Mode)
9
2 1 2b Status Register B
(SRB Model 30 Mode)
9
2 1 3 Digital Output Register
(DOR)
9
2 1 4 Tape Drive Register (TDR)
9
2 1 5 Datarate Select Register
(DRS)
10
2 1 6 Main Status Register
(MSR)
10
2 1 7 FIFO (Data)
11
2 1 8a Digital Input Register
(DIR PC-AT Mode)
11
2 1 8b Digital Input Register
(DIR PS 2 Mode)
11
2 1 8c Digital Input Register
(DIR Model 30 Mode)
12
2 1 9a Configuration Control
Register
(CCR PC AT and PS 2 Modes)
12
2 1 9b Configuration Control
Register
(CCR Model 30 Mode)
12
2 2 RESET
12
2 2 1 Reset Pin (‘‘Hardware’’)
Reset
12
2 2 2 DOR Reset vs DSR Reset
(‘‘Software’’ Reset)
12
CONTENTS
2 3 DMA Transfers
PAGE
12
3 0 DRIVE INTERFACE
12
3 1 Cable Interface
13
3 2 Data Separator
13
3 2 1 Jitter Tolerance
14
3 2 2 Locktime (tLOCK)
14
3 2 3 Capture Range
14
3 2 4 Reference Filter
15
3 3 Write Precompensation
15
4 0 CONTROLLER PHASES
15
4 1 Command Phase
15
4 2 Execution Phase
16
4 2 1 Non-DMA Mode Transfers
from the FIFO to the Host
16
4 2 2 Non-DMA Mode Transfers
from the Host to the FIFO
16
4 2 3 DMA Mode Transfers from
the FIFO to the Host
16
4 2 4 DMA Mode Transfers from
the Host to the FIFO
17
4 2 5 Data Transfer Termination
17
4 3 Result Phase
17
5 0 COMMAND SET DESCRIPTIONS 17
5 1 Data Transfer Commands
24
5 1 1 Read Data
24
5 1 2 Read Deleted Data
25
5 1 3 Read Track
26
5 1 4 Write Data
26
5 1 5 Write Deleted Data
26
5 1 6 Verify
26
5 1 7 Format Track
27
5 1 7 1 Format Fields
28
5 1 8 Scan Commands
29
2
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