A45L9332AF-6 Ver la hoja de datos (PDF) - AMIC Technology

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A45L9332AF-6

256K X 32 Bit X 2 Banks Synchronous Graphic RAM

AMIC Technology 

5. Write Interrupted by Precharge & DQM

A45L9332A Series

CLK

CMD

DQM

DQ

WR

Note 2

PRE

Note 1

D0 D1 D2 D3

Masked by DQM

Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge

interrupt but only another bank precharge of dual banks operation.

6. Precharge

1) Normal Write (BL=4)

CLK

CMD

WR

DQ

D0

D1

3) Read (BL=4)

CLK

CMD

RD

DQ(CL2)

DQ(CL3)

D2

D3

PRE

tRDL

Note 1

2) Block Write

CLK

CMD

DQ

Q0

Q1

PRE

Q2

Q3

Note 2

1

2

Q0

Q1

Q2

Q3

7. Auto Precharge

BW

Pixel

tBPL

Note 1

PRE

1) Normal Write (BL=4)

CLK

CMD

WR

DQ

D0 D1

3) Read (BL=4)

CLK

CMD

RD

DQ(CL2)

D2 D3

Note 3

Auto Precharge Starts

Q0 Q1 Q2 Q3

2) Block Write

CLK

CMD

DQ

(CL 2,3)

BW

Pixel

tBPL

tRP

Note 3

Auto Precharge Starts

DQ(CL3)

Q0 Q1 Q2 Q3

Note 3

Auto Precharge Starts

* Note : 1. tBPL : Block write data-in to PRE command delay.

2. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other active bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

PRELIMINARY (October, 2001, Version 0.1)

22

AMIC Technology, Inc.

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