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A45L9332AF-6

256K X 32 Bit X 2 Banks Synchronous Graphic RAM

AMIC Technology 

A45L9332A Series

12. About Burst Type Control

Basic

MODE

Pseudo-

MODE

Random

MODE

Sequential counting

Interleave counting

Pseudo-

Decrement Sequential

Counting

Pseudo-Binary Counting

Random column Access

tCCD = 1 CLK

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=1,2,4,8 and full page wrap around.

At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting

At MRS A3 = “1”. (See to Interleave Counting Mode)

Starting Address LSB 3 bits A0-2 should be “000” or “111”.@BL=8.

--if LSB = “000” : Increment Counting.

--if LSB= “111” : Decrement Counting.

For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)

--@ write, LSB=”000”, Accessed Column in order 0-1-2-3-4-5-6-7

--@ read, LSB=”111”, Accessed Column in order 7-6-5-4-3-2-1-0

At BL=4, same applications are possible. As above example, at Interleave

Counting mode, by confining starting address to some values, Pseudo-

Decrement Counting Mode can be realized. See the BURST SEQUENCE TABLE

carefully.

At MRS A3 = “0”. (See to Sequential Counting Mode)

A0-2 = “111”. (See to Full Page Mode)

Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be

realized.

--@ Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)

--@ Pseudo-Binary Counting,

Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)

Note. The next column address of 256 is 0

Every cycle Read/Write Command with random column address can realize

Random Column Access.

That is similar to Extended Data Out (EDO) Operation of convention DRAM.

13. About Burst Length Control

Basic

MODE

Special

MODE

Random

MODE

Interrupt

MODE

At MRS A2,1,0 = “000”.

1

At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = “001”.

2

At auto precharge, tRAS should not be violated.

4

At MRS A2,1,0 = “010”

8

At MRS A2,1,0 = “011”.

Full Page

At MRS A2,1,0 = “111”.

Wrap around mode (Infinite burst length) should be stopped by burst stop,

RAS interrupt or CAS interrupt.

BRSW

At MRS A9=”1”.

Read burst = 1,2,4,8, full page/write Burst =1

At auto precharge of write, tRAS should not be violated.

Block Write

8 Column Block Write. LSB A0-2 are ignored. Burst length=1.

tBWC should not be violated.

At auto precharge, tRAS should not be violated.

Burst Stop

tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively

Using burst stop command, it is possible only at full page burst length.

Before the end of burst, Row precharge command of the same bank

RAS Interrupt

Stops read/write burst with Row precharge.

(Interrupted by Precharge) tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge, RAS interrupt cannot be issued.

CAS Interrupt

Before the end of burst, new read/write stops read/write burst and starts new

read/write burst or block write.

During read/write burst with auto precharge, CAS interrupt can not be issued.

PRELIMINARY (October, 2001, Version 0.1)

25

AMIC Technology, Inc.

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