A49LF040ATL-33 Ver la hoja de datos (PDF) - AMIC Technology
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A49LF040ATL-33 Datasheet PDF : 32 Pages
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A49LF040
REGISTERS
There are two types of registers available on the A49LF040A,
the General Purpose Inputs Register, and the JEDEC ID
Registers. These registers appear at their respective address
location in the 4 GByte system memory map. Unused
register locations will read as 00H. Any attempt to read or
write any register during an internal Write operation will be
ignored. Refer to Table 7 for the LPC register memory map.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the
state of GPI[4:0] pins at power-up on the A49LF040A. It is
recommended that the GPI[4:0] pins be in the desired state
before LFRAME is brought low for the beginning of the next
bus cycle, and remain in that state until the end of the cycle.
There is no default value since this is a pass-through register.
See Table 8 for the GPI_REG bits and function, and Table 7
for memory address locations for its respective device
strapping.
Table 8: General Purpose Inputs Register
Bit
Bit
Name
Function
Pin Number
32-PLCC 32-TSOP
7:5
-
Reserved
-
-
4
GPI[4] GPI_REG Bit 4
30
6
3
GPI[3] GPI_REG Bit 3
3
11
2
GPI[2] GPI_REG Bit 2
4
12
1
GPI[1] GPI_REG Bit 1
5
13
0
GPI[0] GPI_REG Bit 0
6
14
Block Locking Registers
A49LF040A provides software controlled lock protection
through a set of Block Locking registers. The Block Locking
Registers are read/write registers and it is accessible through
standard addressable memory locations specified in Table 7.
See Table 9 for Bit definition of the Block Lock Register.
Write-Lock. The Write-Lock Bit determines whether the
contents of the Block can be modified (using the Program or
Erase Command). When the Write-Lock Bit is set to ‘1’, the
block is write protected; any operations that attempt to
change the data in the block will fail and the Status Register
will report the error. When the Write-Lock Bit is reset to ‘0’,
the block is not write protected through the Locking Register
and may be modified unless write protected through some
other means. If Top Block Lock, TBL , is Low, VIL, then the
Top Block (Block 7) is write protected and cannot be
modified. Similarly, if Write Protect, WP , is Low, VIL, then
the Main Blocks (Blocks 0 to 6) are write protected and
cannot be modified. After power-up or reset the Write-Lock
Bit is always set to ‘1’ (write protected).
Read-Lock. The Read-Lock bit determines whether the
contents of the Block can be read (from Read mode). When
the Read-Lock Bit is set to ‘1’, the block is read protected;
any operation that attempts to read the contents of the block
will read 00h instead. When the Read-Lock Bit is reset to ‘0’,
read operations in the Block return the data programmed into
the block as expected. After power-up or reset the Read-
Lock Bit is always reset to ‘0’ (not read protected).
Lock-Down. The Lock-Down Bit provides a mechanism for
protecting software data from simple hacking and malicious
attack. When the Lock-Down Bit is set to ‘1’, further
modification to the Write-Lock, Read-Lock and Lock-Down
Bits cannot be performed. A reset or power-up is required
before changes to these bits can be made. When the Lock-
Down Bit is reset to ‘0’, the Write-Lock, Read-Lock and Lock-
Down Bits can be changed.
JEDEC ID Registers
The JEDEC ID registers identify the device as A49LF040A
and manufacturer as AMIC in LPC mode. See Table 7 for
memory address locations for its respective JEDEC ID
location.
Table 4: Address Bit Definition
A31:A23
A23
1111 1111b
ID[3]
A22
1 = Memory access
0 = Register access
A21:A19
ID[2:0]
A18:A0
Device memory address
PRELIMINARY (March, 2006, Version 0.1)
9
AMIC Technology, Corp.
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