A49LF040ATL-33 Ver la hoja de datos (PDF) - AMIC Technology
Número de pieza
componentes Descripción
Lista de partido
A49LF040ATL-33 Datasheet PDF : 32 Pages
| |||
A49LF040
Table 2: LPC Read Cycle
Clock
Cycle
Field
Name
Field Contents LAD[3:0]
LAD[3:0]1
Direction
Comments
1
START
0000
IN
LFRAME must be active (low) for the part to respond. Only the last
start field (before LFRAME transitioning high) should be recognized.
CYCTYPE
2
+ DIR
010X
IN
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
3-10 ADDRESS
YYYY
Address Phase for Memory Cycle. LPC protocol supports a 32-bit
IN
address phase. YYYY is one nibble of the entire address. Addresses
are transferred most-significant nibble first. See Table 4 for address
bits definition and Table 5 for valid memory address range.
11
TAR0
1111
IN
In this clock cycle, the host has driven the bus to all 1s and then floats
Then Float the bus. This is the first part of the bus “turnaround cycle.”
Float
12
TAR1
1111(float)
The A49LF040A takes control of the bus during this cycle.
Then OUT
13
SYNC
0000
OUT
The A49LF040A outputs the value “0000b” indicating that data will be
available during the next clock cycle.
14
DATA
ZZZZ
OUT This field is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT This field is the most-significant nibble of the data byte.
16
TAR0
1111
OUT
In this clock cycle, the A49LF040A drives the bus to all ‘1’s and then
Then Float floats the bus. This is the first part of the bus “turnaround cycle”.
Float
17
TAR1
1111(float)
Host resumes control of the bus during this cycle.
Then IN
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Single-Byte Read Waveforms
LCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
START
CYCTYPE +
DIR
ADDRESS
TAR0 TAR1 SYNC
DATA
TAR0 TAR1
PRELIMINARY (March, 2006, Version 0.1)
6
AMIC Technology, Corp.
Share Link: 