A49LF040ATL-33 Ver la hoja de datos (PDF) - AMIC Technology
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A49LF040ATL-33 Datasheet PDF : 32 Pages
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A49LF040A
Address out of range: The A49LF040A will only response to
address range as specified in Table 4. Address A22 has the
special function of directing reads and writes to the flash
memory (A22=1) or to the register space (A22=0).
ID mismatch: The A49LF040A will compare ID bits in the
address field with the hardware ID strapping. If there is a
mismatch, the device will ignore the cycle. Refer to Table 6
Multiple Device Selection Configuration for detail.
Device Memory Hardware Write Protection
The Top Boot Lock ( TBL ) and Write Protect ( WP ) pins are
provided for hardware write protection of device memory in
the A49LF040A. The TBL pin is used to write protect the top
boot block (64 Kbytes) at the highest flash memory address
range for the A49LF040A. WP pin write protects the
remaining blocks in the flash memory. An active low signal at
the TBL pin prevents Program and Erase operations of the
top boot block. When TBL pin is held high, write protection
of the top boot block is then determined by the Boot Block
Locking register. The WP pin serves the same function for
the remaining blocks of the device memory. The TBL and
WP pins write protection functions operate independently of
one another. Both TBL and WP pins must be set to their
required protection states prior to starting a Program or Erase
operation. A logic level change occurring at the TBL or WP
pin during a Program or Erase operation could cause
unpredictable results. TBL and WP pins cannot be left
unconnected. TBL is internally ORed with the top Boot Block
Locking register. When TBL is low, the top Boot Block is
hardware write protected regardless of the state of the Write-
Lock bit for the Boot Block Locking register. Clearing the
Write-Lock bit in the register when TBL is low will have no
functional effect, even though the register may indicate that
the block is no longer locked. WP is internally ORed with the
Block Locking register. When WP is low, the blocks are
hardware write protected regardless of the state of the Write-
Lock bit for the corresponding Block Locking registers.
Clearing the Write-Lock bit in any register when WP is low
will have no functional effect, even though the register may
indicate that the block is no longer locked.
Reset
A VIL on INIT or RST pin initiates a device reset. INIT and
RST pins have the same function internally. It is required to
drive INIT or RST pins low during a system reset to ensure
proper CPU initialization. During a Read operation, driving
INIT or RST pins low deselects the device and places the
output drivers, LAD[3:0], in a high-impedance state. The
reset signal must be held low for a minimal duration of time
TRSTP. A reset latency will occur if a reset procedure is
performed during a Program or Erase operation. See Table
19, Reset Timing Parameters for more information. A device
reset during an active Program or Erase will abort the
operation and memory contents may become invalid due to
data being altered or corrupted from an incomplete Erase or
Program operation. In this case, the device can take up to
TRSTE to abort a Program or Erase operation.
Write Operation Status Detection
The A49LF040A device provides two software means to
detect the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data Polling (I/O7) and
Toggle Bit (I/O6). The End-of-Write detection mode is
incorporated into the LPC Read cycle. The actual completion
of the nonvolatile write is asynchronous with the system;
therefore, either a Data Polling or Toggle Bit read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e.,
valid data may appear to conflict with either I/O7 or I/O6. In
order to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to read the
accessed location an additional two times. If both reads are
valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Data Polling (I/O7)
When the A49LF040A device is in the internal Program
operation, any attempt to read I/O7 will produce the
complement of the true data. Once the Program operation is
completed, I/O7 will produce true data. Note that even though
I/O7 may have valid data immediately following the
completion of an internal Write operation, the remaining data
outputs may still be invalid: valid data on the entire data bus
will appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any attempt
to read I/O7 will produce a ‘0’. Once the internal Erase
operation is completed, I/O7 will produce a ‘1’. Proper status
will not be given using Data Polling if the address is in the
invalid range.
Toggle Bit (I/O6)
During the internal Program or Erase operation, any
consecutive attempts to read I/O6 will produce alternating
‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop.
Multiple Device Selection
The four ID pins, ID[3:0], allow multiple devices to be
attached to the same bus by using different ID strapping in a
system. When the A49LF040A is used as a boot device,
ID[3:0] must be strapped as 0000, all subsequent devices
should use a sequential up-count strapping (i.e. 0001, 0010,
0011, etc.). The ID bits in the address field are inverse of the
hardware strapping. The address bits [A23, A21:A19] for
A49LF004 are used to select the device with proper IDs. See
Table 6 for IDs. The A49LF040A will compare the strapping
values, if there is a mismatch, the device will ignore the
remainder of the cycle and go into standby mode. Since there
is no ID support in A/A Mux mode, to program multiple
devices a stand-alone PROM programmer is recommended.
PRELIMINARY (March, 2006, Version 0.1)
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AMIC Technology, Corp.
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