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AD6426

Enhanced GSM Processor

Analog Devices 

Preliminary Technical Information

In Modes 2 and 3, PLL programming occurs on any of Rx, Tx

and MonEnableEnd through the synthesizer interface.

Additionally, AGC programming, controlled via the DSP, is

performed during RXON.

Table 18. Pin Function in Mode 2

AD6426 Pin

AGCA

AGCB

Function

DSPFLAG0 ô SYNTHEN1

DSPFLAG1

The third mode is for support of the Siemens chipset,

providing an independent AGC enable from SYNTHEN using

the DSP Flag 0. The same serial interface constraints from

Mode 2 apply. Additionally, the output OCE is provided. This

is the Offset Correction Enable, derived from the

RxEnableStartEarly and RxEnableStartLate timing signals as

shown in Figure 9.

Table 19. Pin Function in Mode 3

AD6426 Pin

AGCA

AGCB

Function

DSPFLAG0

OCE

RxEnableStartEarly

RxEnableStartLate

RXON

OCE

Figure 9. OCE Signal

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 26 -

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