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AD6426

Enhanced GSM Processor

Analog Devices 

Preliminary Technical Information

TEST INTERFACE

The AD6426 provides a complete JTAG test interface. The

functionality of these pins are shown in Table 20.

Furthermore, these pins can assume a different functionality

described in detail in the chapter MODES OF OPERATION.

Table 20. Test Interface

Name

JTAGEN

TCK

TMS

TDI

TDO

I/O Function

I JTAG enable (internal pull

down resistor)

I JTAG test clock input

I JTAG test mode select

I JTAG test data input

O JTAG test data output

JTAG Port

The AD6426 provides full IEEE 1149.1 compliance. The

JTAG Port must be run at a frequency of 5 MHz or less.

The JTAG Port is explicitly enabled through JTAGEN. When

disabled, the corresponding pins are re-used for the AD6426

Feature Modes. The JTAG interface implements four registers

shown in Figure 10. The content of the Instruction register

selects one of these four registers.

Boundary Register

162

163

161

3

Bypass Register

1

2

1

TDI

Bist Register

TDO

8

7

65

4

3

2

1

4

1

Instruction Register

3

2

Figure 10. JTAG Registers

The instruction register contains 4 bits, and supports the

instructions listed in Table 21.

Instruction register values 01XX all select the bypass register

when JTAG compliance is enabled. Values 00XX control the

AD6426 I/O as defined in Mode A, and therefore should not

be used in any other mode.

AD6426

Instr.

Register

4321

0000

0001

0010

0011

0100-

0101

0110

0111

1000-

1110

1111

Table 21. JTAG Instructions

Code

Comments

ExTest

Clamp

Sample/PreLoad

DoBist

Public Instruction

Optional Public Instruction

Public Instruction

Private Instruction

Engineering Mode Test

Reserved

Mode D

Bypass

Bypass

Private Instruction

H8 Emulation

Reserved

Public Instruction

Selects Mode A

Public Instruction

Selects Mode A (default)

ExTest Instruction

The ExTest instruction is used to force input or output

conditions on the boundary scan cell.

Clamp Instruction

This optional public instruction is similar to the Bypass

instruction, except that once loaded, it will force the values

held in the boundary scan chain onto the corresponding

outputs of the device. This enables all output and bi-

directional pads to be fixed, allowing other parts on the PC-

board to be tested without interference from the AD6426,

while at the same time selecting the Bypass register for the

shortest possible scan path.

All input activity to the AD6426 will be ignored during this

time, since all inputs are driven from the preloaded values in

the boundary scan chain. Typically therefore this instruction

would be preceded by the Sample/Preload instruction. This

instruction is only valid during the normal operation of the

AD6426; i.e. in Mode A.

Sample/Preload Instruction

The Sample/Preload instruction is fully IEEE compliant.

Boundary Register

The boundary cell structure is based on the I/O definition in

Mode A, and hence pins which are outputs only in this mode,

but become inputs in another mode, do not support input scan

cells, and vice versa. Table 22 shows the complete Boundary

register.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 27 -

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