AD73322 Ver la hoja de datos (PDF) - Analog Devices
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AD73322 Datasheet PDF : 43 Pages
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AD73322
SPECIFICATIONS1 (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
AD73322A
Min Typ
Max Units Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.2
2.4
50
130
1.2
2.4
2
V
5VEN = 0
V
5VEN = 1
ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
Ω
V
5VEN = 0, Unloaded
V
5VEN = 1, Unloaded
kΩ
5VEN = 1
100 pF
INPUT AMPLIFIER
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
± 1.0
3.156
50
100
mV
V
Max Output Swing = (3.156/2.4) × VREFCAP
kΩ
fC = 32 kHz
pF
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk ADC-to-DAC
ADC-to-ADC
DC Offset
Power Supply Rejection
Group Delay4, 5
Input Resistance at PGA2, 4, 6
+1
–1
5
±1
1.0
0.5
3.156
3.17
2.1908
0
0.4
–0.7
± 0.1
78
78
57
56
–84
–70
–65
–71
–100
–100
–70
+10
–65
25
20
Bits
%
µs
µs
V p-p
dBm
V p-p
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm0
dB
dB
dB
mV
dB
µs
kΩ
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
5VEN = 1
Measured Differentially
Max Input Swing = (3.156/2.4) × VREFCAP
Measured Differentially
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 7
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 8 kHz
0 Hz to fSAMP/2; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Output Sample Rate
Input Amplifiers Bypassed
REV. B
–5–
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