AD73322 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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Lista de partido
AD73322 Datasheet PDF : 43 Pages
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AD73322
VREFCAP
VREFOUT
ADC
DAC
Maximum Input Range
at VIN
Nominal Reference Level
Maximum Voltage
Output Swing
Single-Ended
Differential
Nominal Voltage
Output Swing
Single-Ended
Differential
Output Bias Voltage
Table III. Signal Ranges
3 V Power Supply
5VEN = 0
1.2 V ± 10%
1.2 V ± 10%
5 V Power Supply
5VEN = 0
5VEN = 1
1.2 V
2.4 V
1.2 V
2.4 V
1.578 V p-p
1.0954 V p-p
1.578 V p-p
1.0954 V p-p
3.156 V p-p
2.1908 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
3.156 V p-p
6.312 V p-p
2.1908 V p-p
4.3818 V p-p
VREFOUT
TIMING CHARACTERISTICS (AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
Parameter
Limit at
TA = –40؇C to +85؇C
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Specifications subject to change without notice.
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
–8–
REV. B
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