AD7891(RevA) Ver la hoja de datos (PDF) - Analog Devices
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AD7891 Datasheet PDF : 20 Pages
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AD7891
TIMING CHARACTERISTICS1, 2
Parameter
A, B, Y Versions
Units
Test Conditions/Comments
tCONV
1.6
Parallel Interface
t1
0
t2
35
t3
25
t4
5
t5
0
t6
35
t7
55
t8
35
t93
25
t104
5
30
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Conversion Time
CS to RD/WR Setup Time
Write Pulsewidth
Data Valid to Write Setup Time
Data Valid to Write Hold Time
CS to RD/WR Hold Time
CONVST Pulsewidth
EOC Pulsewidth
Read Pulsewidth
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
Serial Interface
t11
30
t123
20
t13
25
t14
25
t153
5
t163
15
t17
20
t184
0
30
t18A4
0
30
t19
20
t20
15
t21
10
t22
30
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS Low to SCLK Falling Edge Hold Time
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of +5 V) and timed from a voltage level of +1.6 V.
2See Figures 2, 3 and 4.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8␣ V or 2.4␣ V.
4These times are derived from the measured time taken by the data outputs to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN
50pF
+1.6V
200A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. A
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