AD7891(RevA) Ver la hoja de datos (PDF) - Analog Devices

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AD7891
(Rev.:RevA)

LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System

Analog Devices 

AD7891

PARALLEL INTERFACE MODE FUNCTIONS

Mnemonic

Description

CS

Chip Select Input. Active low logic input which is used in conjunction with RD to enable the data

outputs and with WR to allow input data to be written to the part.

RD

Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs.

WR

Write Input. Active low, logic input used in conjunction with CS to latch the multiplexer address and

software control information. The rising edge of this input also initiates an internal pulse. When using

the software start facility, this pulse delays the point at which the track/hold goes into hold and con-

version is initiated. This allows the multiplexer to settle and acquisition time of the track/hold to

elapse when a channel address is changed. If the SWCON bit of the control register is set to 1, when

this pulse times out, the track/hold then goes into hold and conversion is initiated. If the SWCON bit

of the control register is set to 0 the track/hold and conversion sequence are unaffected by the WR

operation.

Data I/O Lines

There are 12 data input/output lines on the AD7891. When the part is configured for parallel mode (MODE = 1), the output data

from the part is provided at these 12 pins during a read operation. For a write operation in parallel mode, these lines provide access

to the part’s Control Register.

Parallel Read Operation

During a parallel read operation the 12 lines become the 12 data bits containing the conversion result from the AD7891. These data

bits are labelled Data Bit 0 (LSB) to Data Bit 11 (MSB). They are three-state TTL-compatible outputs. Output data coding is twos

complement when the data FORMAT Bit of the control register is 1 and straight binary when the data FORMAT Bit of the control

register is 0.

Mnemonic

DB0–DB11

Description

Data Bit 0 (LSB) to Data Bit 11 (MSB). Three-state TTL-compatible outputs which are controlled

by the CS and RD inputs.

Parallel Write Operation

During a parallel write operation the following functions can be written to the control register via the 12 data input/output pins.

Mnemonic

Description

A0

A1

A2

SWCON

SWSTBY

FORMAT

Address Input. The status of this input during a parallel write operation is latched to the A0 bit of the

control register (see Control Register section).

Address Input. The status of this input during a parallel write operation is latched to the A1 bit of the

control register (see Control Register section).

Address Input. The status of this input during a parallel write operation is latched to the A2 bit of the

control register (see Control Register section).

Software Conversion Start. The status of this input during a parallel write operation is latched to the

SWCONV bit of the control register (see Control Register section).

Software Standby Control. The status of this input during a parallel write operation is latched to the

SWSTBY bit of the control register (see Control Register section).

Data Format Selection. The status of this input during a parallel write operation is latched to the

FORMAT bit of the control register (see Control Register section).

–8–

REV. A

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