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ADL5562 Datasheet PDF : 21 Pages
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Data Sheet
ADL5562
INPUT AND OUTPUT INTERFACING
The ADL5562 can be configured as a differential-input to
differential-output driver, as shown in Figure 34. The differential
broadband input is provided by the ETC1-1-13 balun transformer,
and the two 34.8 Ω resistors provide a 50 Ω input match for the
three input impedances that change with the variable gain
strapping. The input and output 0.1 μF capacitors isolate the VCC/2
bias from the source and balanced load. The load must equal 200 Ω
to provide the expected ac performance (see the Specifications
section and the Typical Performance Characteristics section).
3.3V
ETC1-1-13 0.1µF A
VIP2
VIP1
R2
50Ω
0.1µF B
VIN1
VIN2
AC
R1
0.1µF
RL
2
0.1µF
RL
2
NOTES
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2.
Figure 34. Differential-Input to Differential-Output Configuration
Table 4. Differential Termination Values for Figure 34
Gain (dB)
R1 (Ω)
R2 (Ω)
6
28.7
28.7
12
33.2
33.2
15.5
40.2
40.2
The differential gain of the ADL5562 is dependent on the
source impedance and load, as shown in Figure 35.
0.1µF
1/2 RS
AC
1/2 RS
0.1µF
VIP2 100Ω
VIP1 200Ω
VIN1 200Ω
VIN2 100Ω
400Ω
400Ω
5Ω 0.1µF
RL
2
5Ω 0.1µF
RL
2
Figure 35. Differential Input Loading Circuit
The differential gain can be determined using the following
formula. The values of RIN for each gain configuration are
shown in Table 5.
AV
400 RL
RIN 10 RL
(1)
Table 5. Values of RIN for Differential Gain
Gain (dB)
RIN (Ω)
6
200
12
100
15.5
66.7
Single-Ended Input to Differential Output
The ADL5562 can also be configured in a single-ended input
to differential output driver, as shown in Figure 36. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 6 with the required terminations
to match to a 50 Ω source using R1 and R2. Note that R1 must
equal the parallel value of the source and R2. The input and
output 0.1 μF capacitors isolate the VCC/2 bias from the source
and the balanced load. The performance for this configuration
is shown in Figure 11, Figure 14, and Figure 20.
3.3V
50Ω
AC
0.1µF A
VIP2
VIP1
R2
VIN1
B
VIN2
+ 0.1µF
R1
0.1µF
RL
2
0.1µF
RL
2
NOTES
1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1
AND INPUT B TO VIN1.
2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2
AND INPUT B TO VIN2.
3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
Figure 36. Single-Ended Input to Differential Output Configuration
Table 6. Single-Ended Termination Values for Figure 36
Gain (dB)
R1 (Ω)
R2 (Ω)
5.6
27
60
11.1
29
69
14.1
30
77
The single-ended gain configuration of the ADL5562 is dependent
on the source impedance and load, as shown in Figure 37.
0.1µF
RS R2
VIP2 100Ω
VIP1 200Ω
VIN1 200Ω
AC
VIN2 100Ω
+ 0.1µF
R1
400Ω
400Ω
5Ω
0.1µF
RL
2
5Ω
0.1µF
RL
2
Figure 37. Single-Ended Input Loading Circuit
Rev. F | Page 15 of 21
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