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AIC1574

5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers

Analog Intergrations 

Pin 25: LGATE: Lower N-MOSFET gate drive pin.

Pin 26: PHASE: Over-current detection pin. Con-

nect the PHASE pin to source of

the external upper N-MOSFET.

This pin detects the voltage drop

across the upper N-MOSFET

RDS(ON) for over-current protection.

Pin 27: UGATE: Connect UGATE to pin of the ex-

n APPLICATION INFORMATIONS

The AIC1574 is designed for microprocessor computer

applications with 3.3V and 5V power, and 12V bias in-

put. This IC has one synchronous PWM controller and

three linear controllers. The PWM controller is des-

igned to regulate the microprocessor core voltage

(VOUT1) by driving 2 MOSFETs (Q1 and Q2) in a syn-

chronous rectified buck converter configuration. The

core voltage is regulated to a level programmed by the

5-bit D/A converter. One of the linear controllers is

designed to regulate the advanced graphic port (AGP)

bus voltage (VOUT2) to a digitally programmable level

1.5V or 3.3V. Selection of either output voltage is

achieved by applying the proper logic level at the SE-

LECT pin. The remaining two linear controllers supply

the 1.5V GTL bus power (VOUT3) and 1.8V memory

power (VOUT4). All linear controllers are designed to

employ an external pass transistor.

The Power-On Reset (POR) function continually moni-

tors the input supply voltage +12V at VCC pin, the 5V

input voltage at OCSET pin, and the 3.3V input at

VAUX pin. The POR function initiates soft-start opera-

tion after all three input supply voltage exceed their

POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. An

internal 25µA current source charges an external ca-

pacitor (CSS) on the SS pin from 0V to 4.5V. The

AIC1574

Pin 28: VCC:

ternal upper N-MOSFET gate.

The chip power supply pin. It also

provides the gate bias charge for

all the MOSFETs controlled by

the IC. Recommended supply

voltage is 12V. The voltage at this

pin is monitored for Power-On-

Reset purpose.

PWM error amplifier reference input (Non-inverting ter-

minal) and output is clamped to a level proportional to

the SS pin voltage. As the SS pin voltage slew from 1V

to 4V, the output clamp generates PHASE pulses of

increasing width that charge the output capacitors. Af-

ter the the output voltage increases to approximately

70% of the set value, the reference input clamp slows

the output voltage rate-to rise and provides a smooth

transition to the final set voltage. Additionally, all linear

regulator’s reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method

provides a rapid and controlled output voltage rise.

Fig. 1 and Fig. 2 show the soft-start sequence for the

typical application. The internal oscillator’s triangular

waveform is compared to the clamped error amplifier

output voltage. As the SS pin voltage increases, the

pulse width on PHASE pin increases. The interval of

increasing pulse width continues until output reaches

sufficient voltage to transfer control to the input refer-

ence clamp.

Each linear output initially follows a ramp. When each

output reaches sufficient voltage the input reference

clamp slows the rate of output voltage rise. The

PGOOD signal toggles ‘high’ when all output voltage

levels have exceeded their under-voltage levels.

Fault Protection

All four outputs are monitored and protected against

12

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