AIC1574 Ver la hoja de datos (PDF) - Analog Intergrations

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AIC1574

5-bit DAC, Synchronous PWM Power Regulator with Triple Linear Controllers

Analog Intergrations 

radiate noise into the circuit, and lead to device

over-voltage stress. Careful component selection

and tight layout of critical components, and short,

wide metal trace minimize the voltage spike.

A ground plane should be used. Locate the input

capacitors (CIN) close to the power switches.

Minimize the loop formed by CIN, the upper

MOSFET (Q1) and the lower MOSFET (Q2) as

possible. Connections should be as wide as short

as possible to minimize loop inductance.

The connection between Q1, Q2 and output induc-

tor should be as wide as short as practical. Since

this connection has fast voltage transitions will ea-

sily induce EMI.

The output capacitor (COUT) should be located as

close the load as possible. Because minimize the

transient load magnitude for high slew rate requires

low inductance and resistance in circuit board

AIC1574

The AIC1574 is best placed over a quiet ground

plane area. The GND pin should be connected to

the groundside of the output capacitors. Under no

circumstances should GND be returned to a ground

inside the CIN, Q1, Q2 loop. The GND and PGND

pins should be shorted right at the IC. This help to

minimize internal ground disturbances in the IC and

prevents differences in ground potential from dis-

rupting internal circuit operation.

The wiring traces from the control IC to the MOS-

FET gate and source should be sized to carry peak

current.

The Vcc pin should be decoupled directly to GND

by a 2.2µF ceramic capacitor, trace lengths should

be as short as possible.

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