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AM79C961AKCW

PCnet™-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

2) DRQ inactive to MASTER* inactive time

Description: The data sheet lists a minimum limit of 40ns for the time that DRQ goes inactive until MASTER* goes

inactive. During the course of device characterization a minimum value of less than 40ns has been observed.

The lower limit for this parameter therefore has been changed to 30ns. (DRQ inactive to MASTER* inactive time).

Implication: There is no jeopardy because of this change. The device tristates its active command, SBHE, SA, and

LA lines before MASTER* goes inactive.

Work-around: None required.

Status: Data sheet limit will be changed. There will be no change to the silicon.

3) DRQ inactive to Command, SBHE*, SA0-9 and LA17-23 tristated.

Description: The data sheet lists a maximum limit of 0ns for the time that DRQ goes inactive until Command,

SBHE*, SA0-9 and LA17-23 signals tristate. During the course of device characterization a maximum value of more

than 0ns has been observed. The upper limit for this parameter therefore has been changed to 10ns. (DRQ inactive

to Command, SBHE*, SA0-9 and LA17-23 tristated)

Implication: There is no jeopardy because of this change. The MASTER* which controls the IO on the bus goes

inactive after this time.

Work-around: None required.

Status: Data sheet limit will be changed. There will be no change to the silicon.

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Am79C961A

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