CMX605(2001) Ver la hoja de datos (PDF) - CML Microsystems Plc
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CMX605 Datasheet PDF : 27 Pages
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Digital Line to POTS Interface
CMX605
1.5.4 SPM Generator
This block operates independently and has its own output pin. It can transmit 12kHz or 16kHz and is
controlled by bit 4 of the SETUP Register. Bit 7 of the MODE Register is used to enable or disable this
block. The signal has a rise and fall time each of about 4.5ms. The SPM signal rises from the bias level
to 0dBm in 16 steps of »2dB magnitude, and falls from 0dBm to bias level in 16 steps of »2dB
magnitude.
1.5.5 Transmit Signal Control
This block adjusts the amplitude of the FSK transmit signal output level, the level skew between DTMF
tones and the signal routing to the output ports.
Output signal levels are proportional to VDD. The nominal output signal levels (at 0dB attenuation and
VDD = 5.0V) are:
Single Tone
Dual Tone (per tone)
DTMF High Frequency Tone
DTMF Low Frequency Tone
FSK Signal
0dBm
-3dBm
-3dBm
-5dBm
0dBm
The RING signal is digital: a square wave with amplitude of ≈ VDD peak to peak. When the RING signal
is not selected, the RING output pin is connected to VSS.
The level attenuator provides for level adjustment from 0dB to -14dB in -2dB steps. The typical level is
determined by bits 2 to 4 of the MODE Register as shown in the table below:
MODE Register
Bit 4 Bit 3
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit 2
0
1
0
1
0
1
0
1
Signal Level Adjustment
(dB)
0
-2
-4
-6
-8
-10
-12
-14
1.5.6 Tx UART
This block connects the µC, via the ‘C-BUS’ interface, to the FSK Encoder.
The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters
by adding Start and Stop bits. The transmit data is then passed to the FSK Encoder.
Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready
bit (bit 6) of the STATUS Register goes high. It will then be treated by the Tx UART block in one of two
ways, depending on the setting of bit 1 of the SETUP Register:
If bit 1 of the SETUP Register is ‘0’ (Tx Sync mode) then the 8 bits from the TX DATA Register
will be transmitted sequentially at 1200bps, lsb (D0) first.
If bit 1 of the SETUP Register is ‘1’ (Tx Async mode) then bits will be transmitted as
asynchronous data characters at 1200 bps according to the following format:
© 2001 Consumer Microcircuits Limited
10
D/605/6
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