CMX605(2001) Ver la hoja de datos (PDF) - CML Microsystems Plc

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CMX605
(Rev.:2001)

Digital Line to POTS Interface

CML Microsystems Plc 

Digital Line to POTS Interface

CMX605

One Start bit (Space)

Eight Data bits (D0-D7) from the TX DATA Register, with the lsb (D0) transmitted first

One Stop bit (Mark)

Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data

Underflow) of the STATUS Register being set to ‘1’. If the ‘Tx Async’ mode of operation is selected then

a continuous Mark (‘1’) signal will be transmitted until a new value is loaded into TX DATA. If the ‘Tx

Sync’ mode is selected then the byte already in the TX DATA Register will be re-transmitted.

Figure 3a Transmit UART Function (Async)

Figure 3b Transmit UART Function (Sync)

© 2001 Consumer Microcircuits Limited

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D/605/6

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