CY7C008V(2010) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C008V
(Rev.:2010)

3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No.1 (Either Port Address Access)[23, 24, 25]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No.2 (Either Port CE/OE Access)[23, 26, 27]

CE

OE

DATA OUT

ICC

CURRENT ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[23, 25, 26, 27]

tRC

ADDRESS

tAA

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

CY7C008V/009V

CY7C018V/019V

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

Notes

23. R/W is HIGH for read cycles.

24. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

25. OE = VIL.

26. Address valid prior to or coincident with CE transition LOW.

27. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document Number: 38-06044 Rev. *E

Page 11 of 23

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