CY7C008V(2010) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C008V
(Rev.:2010)

3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM

Cypress Semiconductor 

CY7C008V/009V

CY7C018V/019V

Switching Waveforms (continued)

Busy Timing Diagram No. 1 (CE Arbitration)[41]

CEL Valid First:

ADDRESSL,R

ADDRESS MATCH

CEL

CER

BUSYR

CER Valid First:

tPS

tBLC

tBHC

ADDRESSL,R

CER

CEL

BUSYL

ADDRESS MATCH

tPS

tBLC

tBHC

Busy Timing Diagram No. 2 (Address Arbitration)[41]

Left Address Valid First:

ADDRESSL

tRC or tWC

ADDRESS MATCH

tPS

ADDRESSR

BUSYR

tBLA

ADDRESS MISMATCH

tBHA

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSYL

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

Note

41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Document Number: 38-06044 Rev. *E

Page 15 of 23

[+] Feedback

Share Link: