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EM638325

2M x 32Sy nchronous DRAM (SDRAM)

Etron Technology 

EtronTech

2Mega x 32 SDRAM EM638325

Pin Descriptions

Table 1. Pin Details of EM638325

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the

positive edge of CLK. CLK also increments the internal burst counter and controls the

output registers.

CKE

Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes

low synchronously with clock(set-up and hold time same as other inputs), the internal clock

is suspended from the next clock cycle and the state of output and burst address is frozen

as long as the CKE remains low. When all banks are in the idle state, deactivating the clock

controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except

after the device enters Power Down and Self Refresh modes, where CKE becomes

asynchronous until exiting the same mode. The input buffers, including CLK, are disabled

during Power Down and Self Refresh modes, providing low standby power.

BS0,

BS1

Input Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or

BankPrecharge command is being applied. BS is also used to program the 11th bit of the

Mode and Special Mode registers.

A0-A10

Input

Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-

A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge)

to select one location out of the 256K available in the respective bank. During a Precharge

command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).

The address inputs also provide the op-code during a Mode Register Set or Special Mode

Register Set command.

CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command

decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external

bank selection on systems with multiple banks. It is considered part of the command code.

RAS#

Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction

with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#

and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate

command or the Precharge command is selected by the WE# signal. When the WE# is

asserted "HIGH," the BankActivate command is selected and the bank designated by BS is

turned on to the active state. When the WE# is asserted "LOW," the Precharge command is

selected and the bank designated by BS is switched to the idle state after the precharge

operation.

CAS#

Input Column Address Strobe: The CAS# signal defines the operation commands in

conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK.

When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by

asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE#

"LOW" or "HIGH."

WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the

RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is

used to select the BankActivate or Precharge command and Read or Write command.

DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls.

DQM3

The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is

masked when DQM is sampled HIGH during a write cycle. Output data is masked (two-

clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31-

DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.

DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of

DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.

Preliminary

3

Rev 1.4

Oct. 2005

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