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ETC5067D-X

SERIAL INTERFACE CODEC/FILTER WITH RECEIVE POWER AMPLIFIER

STMicroelectronics 

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

PIN DESCRIPTION

Name

VPO+

Pin

Type (*)

O

N

Description

1 The Non-inverting Output of the Receive Power Amplifier

GNDA

VPO-

GND

O

2 Analog Ground. All signals are referenced to this pin.

3 The Inverting Output of the Receive Power Amplifier

VPI

I

4 Inverting Input to the Receive Power Amplifier. Also powers down both

amplifiers when connected to VBB.

VFRO

O

5 Analog Output of the Receive Filter.

VCC

S

6 Positive Power Supply Pin. VCC = +5V ±5%

FSR

I

7 Receive Frame Sync Pulse which enable BCLKR to shift PCM data into

DR. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.

DR

I

8 Receive Data Input. PCM data is shifted into DR following the FSR leading

edge

BCLKR/CLKSEL

I

9 The bit Clock which shifts data into DR after the FSR leading edge. May

vary from 64KHz to 2.048MHz.

ct(s) MCKLR/PDN

te Produ MCLKX

le BCLKX

bso DX

O FSX

t(s) - TSX

uc ANLB

Prod GSX

te VFXI-

le VFXI+

soVBB

Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz

or 2.048MHz for master clock in synchronous mode and BCLKX is used

for both transmit and receive directions (see table 1). This input has an

internal pull-up.

I

10 Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May

be asynchronous with MCLKX, but should be synchronous with MCLKX for

best performance. When MCLKR is connected continuously low, MCLKX is

selected for all internal timing. When MCLKR is connected continuously

high, the device is powered down.

I

11 Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May

be asynchronous with MCLKR.

I

12 The bit clock which shifts out the PCM data on DX. May vary from 64KHz

to 2.048MHz, but must be synchronous with MCLKX.

O

13 The TRI-STATE®PCM data output which is enabled by FSX.

I

14 Transmit frame sync pulse input which enables BCLKX to shift out the

PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for

timing details.

O

15 Open drain output which pulses low during the encoder time slot. Must to

be grounded if not used.

I

16 Analog Loopback Control Input. Must be set to logic ’0’ for normal

operation. When pulled to logic ’1’, the transmit filter input is disconnected

from the output of the transmit preamplifier and connected to the VPO+

output of the receive power amplifier.

O

17 Analog output of the transmit input amplifier. Used to set gain externally.

I

18 Inverting input of the transmit input amplifier.

I

19 Non-inverting input of the transmit input amplifier.

S

20 Negative Power Supply Pin. VBB = -5V ±5%

b(*) I: Input, O: Output, S: Power Supply.

OTRI-STATE® is a trademark of National Semiconductor Corp.

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