ETC5067D-X Ver la hoja de datos (PDF) - STMicroelectronics
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ETC5067D-X Datasheet PDF : 18 Pages
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ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
All TIMING SPECIFICATIONS
Symbol
Parameter
Min. Typ. Max. Unit
1/tPM
Frequency of master clocks
MCLKX and MCLKR
Depends on the device used and the
BCLKR/CLKSEL Pin
1.536
2.048
1.544
MHz
tWMH
Width of Master Clock High
MCLKX and MCLKR 160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR 160
ns
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period of Bit Clock
485 488 15.725 ns
tWBH
Width of Bit Clock High (VIH = 2.2 V)
160
ns
tWBL
Width of Bit Clock Low (VIL = 0.6 V)
160
ns
tRB
Rise Time of Bit Clock (tPB = 488 ns)
50
ns
tFB
Fall Time of Bit Clock (tPB = 488 ns)
50
ns
tSBFM
t(s) tHBF
c tSFB
u tHBFI
rod tDZF
te P tDBD
sole tDZC
b tSDB
O tHBD
- tHOLD
t(s) tSF
c tHF
du tXDP
Pro tWFL
Set-up time from BCLKX high to MCLKX falling edge.
100
(first bit clock after the leading edge of FSX)
Holding Time from Bit Clock Low to the Frame Sync
0
(long frame only)
Set-up Time from Frame Sync to Bit Clock (long frame only)
80
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
FSX or FSR 100
Delay Time to valid data from FSX or BCLKX, whichever
20
comes later and delay time from FSX to data output disabled
(CL = 0 pF to 150 pF)
Delay Time from BCLKX high to data valid
0
(load = 150 pF plus 2 LSTTL loads)
Delay Time from BCLKX low to data output disabled
50
Set-up Time from DR valid to BCLKR/X low
50
Hold Time from BCLKR/X low to DR invalid
50
Holding Time from Bit Clock High to Frame Sync (short frame only)
0
Set-up Time from FSX/R to BCLKX/R Low
80
(short frame sync pulse) - Note 1
Hold Time from BCLKX/R Low to FSX/R Low
100
(short frame sync pulse) - Note 1
Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads)
Minimum Width of the Frame Sync Pulse (low level)
160
(64 bit/s operating mode)
ns
ns
ns
ns
165
ns
150
ns
165
ns
ns
ns
ns
ns
ns
140
ns
ns
te Note : 1.For short frame sync timing. FSX and FSR must go high while their respective bit clocks are high.
Obsole Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)
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