M27V402 Ver la hoja de datos (PDF) - STMicroelectronics

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M27V402

4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM

STMicroelectronics 

M27V402

Table 5. AC Measurement Conditions

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

High Speed

≤ 10ns

0 to 3V

1.5V

Standard

≤ 20ns

0.4V to 2.4V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

High Speed

1.3V

3V

1N914

1.5V

0V

3.3kΩ

t(s) Standard

c 2.4V

te Produ 0.4V

2.0V

0.8V

AI01822

DEVICE

UNDER

TEST

CL

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

OUT

AI01823B

bsole Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

- O Symbol

Parameter

t(s) CIN

Input Capacitance

COUT Output Capacitance

uc Note: 1. Sampled only, not 100% tested.

rod DEVICE OPERATION

P The operating modes of the M27V402 are listed in

te the Operating Modes table. A single power supply

le is required in the read mode. All inputs are TTL

levels except for VPP and 12V on A9 for Electronic

so Signature.

bRead Mode

OThe M27V402 has two control functions, both of

Test Condition

VIN = 0V

VOUT = 0V

Min

Max

Unit

6

pF

12

pF

(tAVQV) is equal to the delay from E to output

(tELQV). Data is available at the output after a delay

of tGLQV from the falling edge of G, assuming that

E has been low and the addresses have been

stable for at least tAVQV-tGLQV.

Standby Mode

The M27V402 has a standby mode which reduces

the supply current from 20mA to 20µA with low

which must be logically active in order to obtain voltage operation VCC ≤ 3.6V, see Read Mode DC

data at the outputs. Chip Enable (E) is the power Characteristics table for details. The M27V402 is

control and should be used for device selection. placed in the standby mode by applying a CMOS

Output Enable (G) is the output control and should high signal to the E input. When in the standby

be used to gate data to the output pins, mode, the outputs are in a high impedance state,

independent of device selection. Assuming that independent of the G input.

the addresses are stable, the address access time

4/15

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