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M27V402 Datasheet PDF : 15 Pages
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M27V402
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±10
µA
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
±10
µA
ICC Supply Current
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC = 3.6V
20
mA
ICC1 Supply Current (Standby) TTL
E = VIH
1
mA
ICC2 Supply Current (Standby) CMOS
E > VCC – 0.2V, VCC = 3.6V
20
µA
IPP Program Current
VPP = VCC
10
µA
VIL Input Low Voltage
–0.3
0.8
V
VIH (2) Input High Voltage
2
VCC + 1
V
VOL Output Low Voltage
IOL = 2.1mA
0.4
V
) Output High Voltage TTL
t(s VOH
Output High Voltage CMOS
IOH = –400µA
2.4
V
IOH = –100µA
VCC–0.7V
V
uc Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
d 2. Maximum DC voltage on Output is VCC +0.5V.
Pro Two Line Output Control
te Because EPROMs are usually used in larger
le memory arrays, the product features a 2 line con-
o trol function which accommodates the use of mul-
s tiple memory connection. The two line control
b function allows:
O a. the lowest possible memory power dissipation,
- b. complete assurance that output bus contention
) will not occur.
t(s For the most efficient use of these two control
c lines, E should be decoded and used as the prima-
u ry device selecting function, while G should be
d made a common connection to all devices in the
ro array and connected to the READ line from the
system control bus. This ensures that all deselect-
P ed memory devices are in their low power standby
te mode and that the output pins are only active
le when data is required from a particular memory
Obso device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the de-
vice.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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