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IDT72205LB

CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

WCLK

D0 - D17

WEN

FF

RCLK

t CLKH

t CLK

t CLKL

t DS

DATA IN VALID

tENS

t WFF

t

(1)

SKEW1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t DH

tENH

t WFF

NO OPERATION

REN

2766 drw 08

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If

the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 6. Write Cycle Timing

5.16

10

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