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LAN91C96

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

SMSC -> Microchip 

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

FUNCTION

Interrupt Output

Ethernet Interrupt Source

Ethernet Interrupt Enable

Ethernet Interrupt Status Bit

Table 5.5 - Interrupt Merging

PCMCIA MODE

LOCAL BUS MODE

nIREQ when function is Ready.

Acts as ready line at power up.

I.e. remains low until the chip

(therefore, card) is Ready

INTR0-3

OR function of all interrupt bits specified in the Interrupt Status Register

ANDed with their respective Enable bits

Not Applicable in LOCAL BUS

mode

Intr bit in ECSR

5.3

Reset Logic

The pins and bits involved in the different reset mechanisms are:

RESET - Input Pin

SRESET - Soft Reset bit in ECOR, or the SRESET bit

SOFT RST - EPH Soft Reset bit in RCR

RESET pin

ECOR

Register

SRESET bit

SOFT RST

RESETS THE FOLLOWING

FUNCTIONS

All internal logic

The Ethernet controller function and

Ethernet PCMCIA Configuration Registers

except for the bit itself. Setting this bit also

lowers the nIREQ/READY line. When

cleared, the nIREQ/READY line is raised.

The Ethernet controller itself except for

the IA, CONF and BASE registers. It does

not reset any PCMCIA Configuration

Register.

SAMPLES

LOCAL BUS

VS. PCMCIA

MODE

Yes

No

No

TRIGGERS

EEPROM

READ

Yes

Yes

No

5.4

Power Down Logic States

Table 5.6, Table 5.7, Table 5.8, and Table 5.9 describe the power down states of the LAN91C96. The

pins and bits involved in power down are:

1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).

2. Pwrdwn bits in ECSR

3. Enable Function bit in ECOR

4. PWRDN - Legacy power down bit in Control Register.

SMSC LAN91C965v&3v

Page 31

DATASHEET

Rev. 09/10/2004

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