LAN91C96 Ver la hoja de datos (PDF) - SMSC -> Microchip
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LAN91C96 Datasheet PDF : 125 Pages
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
NO.
WAKES UP BY
4 By writing a 0 to
CTR PWRDWN and
0 to WAKEUP_EN
bits
5 By writing 1 to
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN
6 By writing 1 to
ECOR Func Enable,
0 to ECSR Power
Down, 0 to CTR
PWRDWN, and 0 to
WAKEUP_EN bit
7 By writing 0 to
ECSR Power Down
bit*
7S By writing 0 to
ECSR Power Down
and a 0 to CTR
PWRDWN bit
8 By writing 0 to
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
8S By writing 0 to
ECSR Power Down
and writing CTR
PWRDWN bit = 0 &
WAKEUP_EN = 0, if
needed
PWR DWN PIN
(A= ASSRTD)
nA
nA
nA
nA
nA
nA
nA
NEXT STATE
ECOR
FUNC
ENABLE
ECSR
PWR
DOWN
CTR
PWRDWN
BIT
1
0
0
CTR
WAKEUP_EN
BIT
0
COMMENTS
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
0
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
0
0
Note: Both
Power down
bits need to be
written as 0
only if both
were set to 1
0
1
0
0
0
PCMCIA Attribute Memory
Address 0- 7FFEh
The Attribute Memory is implemented using an external parallel EEPROM, ROM or Flash ROM. A parallel
EEPROM (or equivalent external device) must be used for CIS.
In LOCAL BUS mode, serial EEPROM is used for configuration and IEEE Node address making it software
compatible to the LAN9xxx family of Ethernet LAN Controllers. The EEPROM is optional for both LOCAL BUS
and PCMCIA requiring a Minimum size of 64 X 16 bit word addresses.
The LAN91C96 generates the appropriate control lines (nFCS and nFWE) to read and write the Attribute
memory, and it tri-states the data bus during external Attribute Memory accesses. Only even locations are
used.
Rev. 09/10/2004
Page 34
DATASHEET
SMSC LAN91C965v&3v
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