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LH540215

512 × 18 / 1024 × 18 Synchronous FIFO

Sharp Electronics 

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

In the Enhanced Operating Mode, coordinated op-

eration of two 18-bit FIFOs as one 36-bit FIFO may be

ensured by ‘interlocked’ crosscoupling of the status-

flag outputs from each FIFO to the expansion inputs

of the other one; that is, FF to WXI/WEN2, and EF to

RXI/REN2, in both directions between two paralleled

FIFOs. This ‘interlocked’ operation takes effect

automatically, if two paralleled FIFOs are crosscon-

nected in this manner, with the EMODE control input

being asserted (LOW). (See Tables 1 and 2, also

Figures 27 and 30.) IDT-compatible depth cascading

no longer is available when operating in this ‘inter-

locked-paralleled’ mode; however, pipelined depth

cascading remains available.

68-PIN PLCC

TOP VIEW

D14

D13

D12

D11

D10

D9

VCC

D8

VSS

D7

D6

D5

D4

D3

D2

D1

D0

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

10

60

11

59

12

58

13

57

14

56

15

55

16

54

17

53

18

52

19

51

20

50

21

49

22

48

23

47

24

46

25

45

26

44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

Q14

Q13

VSS

Q12

Q11

VCC

Q10

Q9

VSS

Q8

Q7

EMODE *

Q6

Q5

VSS

Q4

BOLD ITALIC = Enhanced Operating Mode.

* This pin is VCC on IDT pinout; if EMODE pin is simply

biased to VCC, part will behave identical to IDT functionality.

Figure 2. Pin Connections for 68-Pin PLCC Package

540215-2

BOLD ITALIC = Enhanced Operating Mode

3

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