LPC47M172 Ver la hoja de datos (PDF) - SMSC -> Microchip
Número de pieza
componentes Descripción
Lista de partido
LPC47M172 Datasheet PDF : 226 Pages
| |||
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
Chapter 1 General Description.............................................................................................................. 11
Chapter 2 Pin Layout ............................................................................................................................ 12
Chapter 3 Description of Pin Functions ................................................................................................ 14
3.1 Buffer Name Descriptions ..........................................................................................................................22
3.2 Pins With Internal Resistors .......................................................................................................................23
3.3 Pins That Require External Resistors.........................................................................................................23
3.4 Default State of Pins...................................................................................................................................24
Chapter 4 Block Diagram ...................................................................................................................... 28
Chapter 5 Power and Clock Functionality............................................................................................. 29
5.1 3 Volt Operation / 5 Volt Tolerance ............................................................................................................29
5.2 VCC Power ................................................................................................................................................29
5.3 VTR Power.................................................................................................................................................29
5.3.1 Trickle Power Functionality .................................................................................................................30
5.4 V5P0_STBY Power ....................................................................................................................................30
5.5 32.768 kHz Trickle Clock Input...................................................................................................................30
5.5.1 Indication of 32KHZ Clock...................................................................................................................30
5.6 14.318 MHz Clock Input .............................................................................................................................31
5.7 Internal PWRGOOD ...................................................................................................................................31
5.8 Maximum Current Values...........................................................................................................................31
5.9 Power Management Events (PME/SCI) .....................................................................................................31
Chapter 6 Functional Description.......................................................................................................... 32
6.1 Super I/O Registers....................................................................................................................................32
6.2 Host Processor Interface (LPC) .................................................................................................................33
6.3 LPC Interface .............................................................................................................................................33
6.3.1 LPC Interface Signal Definition ...........................................................................................................33
6.3.2 LPC Cycles .........................................................................................................................................33
6.3.3 Field Definitions...................................................................................................................................33
6.3.4 NLFRAME Usage................................................................................................................................34
6.3.5 I/O Read and Write Cycles..................................................................................................................34
6.3.6 DMA Read and Write Cycles ..............................................................................................................34
6.3.7 DMA Protocol ......................................................................................................................................34
6.3.8 Power Management ............................................................................................................................35
6.3.9 SYNC Protocol ....................................................................................................................................35
6.3.10 I/O and DMA START Fields.............................................................................................................36
6.3.11 LPC Transfers .................................................................................................................................36
6.4 Floppy Disk Controller ................................................................................................................................37
6.4.1 FDC Configuration Registers ..............................................................................................................37
6.4.2 FDC Internal Registers........................................................................................................................37
6.4.3 Status Register A (SRA) .....................................................................................................................38
6.4.4 Status Register B (SRB) .....................................................................................................................39
6.4.5 Digital Output Register (DOR).............................................................................................................41
6.4.6 Tape Drive Register (TDR) .................................................................................................................42
6.4.7 Data Rate Select Register (DSR)........................................................................................................43
6.4.8 Main Status Register...........................................................................................................................45
6.4.9 Data Register (FIFO)...........................................................................................................................46
6.4.10 Digital Input Register (DIR)..............................................................................................................47
6.4.11 Configuration Control Register (CCR) .............................................................................................48
6.4.12 Status Register Encoding ................................................................................................................49
6.5 Modes of Operation....................................................................................................................................51
6.5.1 PC/AT Mode .......................................................................................................................................51
6.5.2 PS/2 Mode ..........................................................................................................................................51
6.5.3 Model 30 Mode ...................................................................................................................................51
6.6 DMA Transfers ...........................................................................................................................................51
6.7 Controller Phases.......................................................................................................................................52
6.7.1 Command Phase ................................................................................................................................52
6.7.2 Execution Phase .................................................................................................................................52
6.8 Data Transfer Termination .........................................................................................................................53
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Page 3
DATASHEET
SMSC LPC47M172
Share Link: 