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LPC47M172

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

7.7 EPP 1.9 Read ............................................................................................................................................95

7.8 EPP 1.7 Operation .....................................................................................................................................95

7.8.1 Software Constraints...........................................................................................................................95

7.9 EPP 1.7 Write.............................................................................................................................................96

7.10 EPP 1.7 Read .........................................................................................................................................96

7.10.1 Extended Capabilities Parallel Port .................................................................................................97

7.10.2 Vocabulary.......................................................................................................................................97

7.11 ECP Implementation Standard ...............................................................................................................98

7.11.1 Description.......................................................................................................................................98

7.12 Register Definitions.................................................................................................................................99

7.12.1 Data and ecpAFifo Port .................................................................................................................100

7.12.2 Device Status Register (dsr)..........................................................................................................101

7.12.3 Device Control Register (dcr) ........................................................................................................101

7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................102

7.12.5 ECPDFIFO (ECP Data FIFO) ........................................................................................................102

7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................102

7.12.7 cnfgA (Configuration Register A) ...................................................................................................103

7.12.8 cnfgB (Configuration Register B) ...................................................................................................103

7.12.9 ecr (Extended Control Register) ....................................................................................................103

7.13 Operation..............................................................................................................................................106

7.13.1 Mode Switching/Software Control..................................................................................................106

7.14 ECP Operation .....................................................................................................................................106

7.15 Termination from ECP Mode ................................................................................................................107

7.16 Command/Data.....................................................................................................................................107

7.17 Data Compression ................................................................................................................................107

7.18 Pin Definition ........................................................................................................................................107

7.19 LPC Connections..................................................................................................................................108

7.20 Interrupts ..............................................................................................................................................108

7.21 FIFO Operation.....................................................................................................................................108

7.21.1 DMA Transfers ..............................................................................................................................109

7.21.2 DMA Mode - Transfers from the FIFO to the Host.........................................................................109

7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................109

7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................109

7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................110

7.22 Power Management..............................................................................................................................110

7.23 Serial IRQ .............................................................................................................................................110

7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................110

7.23.2 SER_IRQ Cycle Control ................................................................................................................111

7.23.3 SER_IRQ Data Frame...................................................................................................................112

7.23.4 Stop Cycle Control.........................................................................................................................112

7.23.5 Latency ..........................................................................................................................................113

7.23.6 EOI/ISR Read Latency ..................................................................................................................113

7.23.7 AC/DC Specification Issue ............................................................................................................113

7.23.8 Reset and Initialization ..................................................................................................................113

7.24 Interrupt Generating Registers .............................................................................................................113

7.25 8042 Keyboard Controller Description ..................................................................................................114

7.25.1 Keyboard Interface ........................................................................................................................114

7.25.2 Keyboard Data Write .....................................................................................................................115

7.25.3 Keyboard Data Read .....................................................................................................................115

7.25.4 Keyboard Command Write ............................................................................................................115

7.25.5 Keyboard Status Read ..................................................................................................................115

7.25.6 CPU-to-Host Communication ........................................................................................................115

7.25.7 Host-to-CPU Communication ........................................................................................................115

7.25.8 KIRQ..............................................................................................................................................115

7.25.9 MIRQ .............................................................................................................................................116

7.25.10 External Keyboard and Mouse Interface .......................................................................................116

7.25.11 Keyboard Power Management ......................................................................................................116

7.25.12 Soft Power Down Mode.................................................................................................................116

7.25.13 Hard Power Down Mode ...............................................................................................................116

7.25.14 Interrupts .......................................................................................................................................117

SMSC/Non-SMSC Register Sets (Rev. 01-11-07)

Page 5

DATASHEET

SMSC LPC47M172

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