datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

LXT332 Ver la hoja de datos (PDF) - Level One

Número de pieza
componentes Descripción
Lista de partido
LXT332 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
/;7êêë 'XDO 7ìî(ì /LQH ,QWHUIDFH 8QLW ZLWK &U\VWDOðOHVV -LWWHU $WWHQXDWLRQ
7DEOH êã +DUGZDUH 0RGH 3LQ DQG %LSRODU +DUGZDUH 0RGH 3LQ 'HVFULSWLRQVì ¤ FRQWLQXHG
3LQ
3LQ 6\PERO ,î2ë
4)3 3/&&
'HVFULSWLRQ
ëí
ëç
LOS1 DO Loss of Signal - Port 1. LOS goes High when 175 consecutive spaces have
been detected. LOS returns to a logic 0 when the received signal reaches a
mark density of 12.5% (refer to LOS0 signal description for details).
ëì
ëæ LLOOP1 DI Local Loopback Enable - Port 1. (RLOOP1 must be Low for LLOOP1 to
occur.)
ëë
ëå
TAOS1 DI Transmit All Ones Enable - Port 1. (RLOOP1 must be Low for TAOS1 to
occur.)
ëê
ëä TRING1 AO Transmit Ring - Port 1. The tip and ring pins for each port are differential
ëç
êë
TTIP1 AO driver outputs designed to drive a 35 - 200 load. Line matching resistors
and transformers can be selected to give the desired pulse height. See Figures
19 through 21.
ëé
êí
TVCC1 AI + 5 volt power supply input for the port 1 transmit driver. TVCC1 must not
vary from TVCC0 or VCC by more than ± 0.3 V.
ëè
êì
TGND1 – Ground. Ground return for power supply TVCC1.
ëæ
êê
VCC AI +5 VDC power supply input for all circuits, except the transmit drivers.
ëå
êé
JASEL DI Jitter Attenuation Select. Selects jitter attenuation for both ports. When
JASEL = 1, JA circuits are placed in the receive paths. When JASEL = 0, JA
circuits are placed in the transmit paths. When JASEL is clocked with MCLK,
the JA circuit is disabled.
ëä
êè
LEN01 DI Line Length Equalizer inputs - Port 1. These pins determine the shape and
êí
êç
LEN11 DI amplitude of the transmit pulse.
êì
êæ
LEN21 DI
êë
êå RLOOP1 DI Remote Loopback Enable - Port 1. (LLOOP1 must = 0 for RLOOP to
occur.)
êê
êä
RCLK1 DO Receive Clock - Port 1. This clock is recovered from the twisted-pair input
signal. Under Loss of Signal (LOS) conditions, this output is derived from
MCLK.
êé
éí
RPOS1 DO Receive Data Positive and Negative - Port 1. In the Bipolar I/O mode, these
(Bipolar)
pins are the data outputs from port 1. A signal on RPOS corresponds to
êè
éì
receipt of a positive pulse on RTIP/RRING. A signal on RNEG corresponds
RNEG1 DO to receipt of a negative pulse on RTIP/RRING. RNEG/RPOS outputs are
(Bipolar)
Non-Return-to-Zero (NRZ). RPOS and RNEG are stable and valid on the ris-
ing edge of RCLK.
êç
éë
TNEG1 DI Transmit Data Positive and Negative - Port 1. In the Bipolar I/O mode,
these pins are TPOS and TNEG, the positive and negative sides of a bipolar
êæ
éê
TPOS1 DI input pair for port 1. Data to be transmitted onto the twisted-pair line is input
at these pins. However, when the TRSTE pin is clocked by MCLK, the
LXT332 switches to a unipolar mode. Unipolar mode pin functions are
described separately.
êå
éé
TCLK1 DI Transmit Clock - Port 1. 1.544 MHz for T1, 2.048 MHz for E1. The trans-
mit data inputs are sampled on the falling edge of TCLK.
ì 7DEOH é GHVFULEHV WKH SLQV XVHG LQ 8QLSRODU +DUGZDUH 0RGHï
ëï ', 'LJLWDO ,QSXWâ '2 'LJLWDO 2XWSXWâ ',î2 'LJLWDO ,QSXWî2XWSXWâ $, $QDORJ ,QSXWâ $2 $QDORJ 2XWSXW
ëðììç
L1

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]