LXT332 Ver la hoja de datos (PDF) - Level One

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LXT332

Dual T1/E1 Line Interface Unit with Crystal-less Attenuation

Level One 

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TPOS0 DI Transmit Positive and Negative Data - Port 0. In the Bipolar I/O mode,

(Bipolar)

these pins are the positive and negative sides of a bipolar input pair for port

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TNEG0

0. Data to be transmitted onto the twisted-pair line is input at these pins.

DI However, when the TRSTE pin is clocked by MCLK, the LXT332 switches

(Bipolar)

to a unipolar mode. Table 2 describes Unipolar mode pin functions.

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RNEG0 DO Receive Positive and Negative Data - Port 0. In the Bipolar I/O mode,

(Bipolar)

these pins are the data outputs from port 0. A signal on RNEG corresponds

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RPOS0

to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corre-

DO sponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS outputs

(Bipolar)

are Non-Return-to-Zero (NRZ). In Host mode, CLKE determines the clock

edge at which these outputs are stable and valid.

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RCLK0 DO Receive Clock - Port 0. This clock is recovered from the input signal.

Under Loss of Signal (LOS) conditions, this output is derived from MCLK.

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SCLK DI Serial Clock. The Serial Clock shifts data into or out from the serial inter-

face register of the selected port.

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VCQ0 DI/O Provides Violation insert, High Frequency Clock, or QRSS generation/detec-

tion functions for Port 0. Pin operation is determined by the VCQE pin.

Violation Insertion Function. When the Violation insertion function is

enabled, this pin is sampled on the falling edge of TCLK to control bipolar

violation (BPV) insertion. If High, a BPV is inserted at the next available

mark transmitted from port 0. A Low-to-High transition is required for each

subsequent violation insertion. (B8ZS and HDB3 zero suppression codes are

not violated.)

Clock Function. When the Clock function is enabled, this pin outputs a

High Frequency Clock (12.352 MHz for T1, 16.384 MHz for E1) tied to the

jitter attenuated clock of port 0. If no JA clock is available, HFC is locked to

the 8x receive timing recovery clock.

Quasi Random Signal Source (QRSS) Function. When the QRSS function

is enabled, a High on this pin enables the QRSS detection circuit and causes

the LXT332 to transmit the QRSS pattern onto the twisted-pair line from

port 0. For error-free QRSS transmission, TPOS0 must be held Low. To

insert errors into the pattern, TPOS must transition from Low to High (TPOS

is sampled on the falling edge of MCLK). A Low-to-High transition is

required for each subsequent violation insertion. (B8ZS and HDB3 zero

suppression codes are not violated.)

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INT1 DO Interrupt Outputs. The interrupt outputs go Low to flag the host processor

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INT0 DO that the respective port has changed state. INT0 and INT1 are open drain

outputs. Each must be tied to VCC through a resistor.

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MCLK DI Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1)

input must be independent, free-running, continuously active and jitter free

for receiver operation. Since the transceivers derive their RCLK timing from

the MCLK input on Loss of Signal (LOS), MCLK cannot be derived from

RCLK.

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GND

– Ground. Ground return for power supply VCC.

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