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M95128-DW3/P

128 Kbit Serial SPI bus EEPROM with high speed clock

STMicroelectronics 

M95128, M95128-W, M95128-R

5

Instructions

Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically

deselects itself.

Table 3. Instruction set

Instruction

Description

WREN

Write Enable

WRDI

Write Disable

RDSR

WRSR

Read Status Register

Write Status Register

READ

Read from Memory Array

WRITE

Write to Memory Array

Instruction Format

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

5.1

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven Low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

High.

Figure 5. Write Enable (WREN) sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

13/41

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