M95128-DW3/P Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Lista de partido

M95128-DW3/P

128 Kbit Serial SPI bus EEPROM with high speed clock

STMicroelectronics 

Instructions

M95128, M95128-W, M95128-R

Table 5. Protection modes

W Signal

SRWD

Bit

Mode

Write Protection of the

Memory Content

Status Register

Protected Area(1) Unprotected Area(1)

1

0

Status Register is

0

1

0

1

Writable (if the WREN

Software instruction has set the

Protected WEL bit)

(SPM) The values in the BP1

and BP0 bits can be

Write Protected

Ready to accept Write

instructions

changed

Status Register is

Hardware write

0

1

Hardware protected

Protected

(HPM) The values in the BP1

Write Protected

Ready to accept Write

instructions

and BP0 bits cannot be

changed

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.

The protection features of the device are summarized in Table 2.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

● If Write Protect (W) is driven High, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

● If Write Protect (W) is driven Low, it is not possible to write to the Status Register even

if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,

are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

● or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP1, BP0) bits of the Status Register, can be used.

18/41

Share Link: